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| == CXD9963GB == | | == CXD9963GB == |
| <div style="float:right">[[File:CXD9963GB-SB-GRID-bw-chipview.png|200px|thumb|left|CXD9963GB, padlayout<br />SB chip view facing BGA<br />A1 marker:northeast/topright]]<br />[[File:CXD9963GB-SB-GRID-bw-pcbview.png|200px|thumb|left|CXD9963GB, padlayout<br />PCB view facing BGA<br />A1 marker:northwest/topleft]]<br />[[File:REX-001 South Bridge pad layout.jpg|200px|thumb|left|REX-001 South Bridge pad layout]]<br />[[File:CXD9963GB Bottom.jpg|200px|thumb|left|CXD9963GB Bottom]]<br />[[File:CXD9963GB.jpg|200px|thumb|left|CXD9963GB (SouthBridge)]]<br />[[File:CXD9963GB-PS3slim.jpg|200px|thumb|left|CXD9963GB (SouthBridge)]]<br />[[File:CXD9963GB-desoldered-form-JSD001.jpg|200px|thumb|left|CXD9963GB (Desoldered)]]</div> | | <div style="float:right">[[File:CXD9963GB-PS3slim.jpg|200px|thumb|left|CXD9963GB (SouthBridge)]]</div> |
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| *Used on: | | *Used on PS3 models: |
| **PS3 Slim [[CECH-20xx]]A/B with motherboard [[DYN-001]] | | **[[CECH-20xx]] with motherboard [[DYN-001]] |
| **PS3 Slim [[CECH-21xx]]A/B with motherboard [[SUR-001]] | | **[[CECH-21xx]] with motherboard [[SUR-001]] |
| **PS3 Slim [[CECH-25xx]]A/B with motherboard [[JTP-001]] or [[JSD-001]] | | **[[CECH-25xx]] with motherboard [[JTP-001]] or [[JSD-001]] |
| **PS3 Slim [[CECH-30xx]]A/B with motherboard [[KTE-001]] | | **[[CECH-30xx]] with motherboard [[KTE-001]] |
| **PS3 Super Slim [[CECH-40xx]]B with motherboard [[MSX-001]] | | **[[CECH-40xx]] with motherboard [[MSX-001]] <!-- and PPX-001 PQX-001 --> |
| **PS3 Super Slim [[CECH-43xx]]A/B with motherboard [[REX-001]] | | **[[CECH-43xx]] with motherboard [[REX-001]] <!-- and RTX-001 ---> |
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| As these [[Motherboard Revisions]]/[[SKU Models]] do not have an [[USB]] hub chip, the frontports are directly connected to this [[South Bridge]] | | As these [[Motherboard Revisions | motherboards]] do not have an [[USB]] hub chip, the two frontports are directly connected to this [[South Bridge]] |
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| | === Gallery === |
| | <gallery> |
| | File:CXD9963GB.jpg|CXD9963GB (SouthBridge) |
| | File:CXD9963GB-desoldered-form-JSD001.jpg|CXD9963GB (Desoldered) |
| | File:REX-001 South Bridge pad layout.jpg|REX-001 South Bridge pad layout |
| | File:CXD9963GB Bottom.jpg|CXD9963GB Bottom |
| | File:CXD9963GB-SB-GRID-bw-chipview.png|CXD9963GB, padlayout<br>SB chip view facing BGA<br>A1 marker:northeast/topright |
| | File:CXD9963GB-SB-GRID-bw-pcbview.png|CXD9963GB, padlayout<br>PCB view facing BGA<br>A1 marker:northwest/topleft |
| | </gallery> |
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| == Pinout == | | == Pinout == |
| {|class="wikitable sortable"
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| ! Pad# !! Name !! Port !! class="unsortable" | Description
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| | A4 || WIFI_DATA_1 || ? || Connected to wifi/BT module. See: [[Media:KTE-001_wifitraces.jpg|wifi/BT 10x7 pinout]] or [[Media:REX-001_wifitraces.jpg|wifi/BT 9x7 pinout]]
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| | B4 || WIFI_DATA_2 || ? || Connected to wifi/BT module. See: [[Media:KTE-001_wifitraces.jpg|wifi/BT 10x7 pinout]] or [[Media:REX-001_wifitraces.jpg|wifi/BT 9x7 pinout]]
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| | F1 || WIFI_CTRL || ? || Connected to wifi/BT module. See: [[Media:KTE-001_wifitraces.jpg|wifi/BT 10x7 pinout]] or [[Media:REX-001_wifitraces.jpg|wifi/BT 9x7 pinout]]
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| | U18 || SB_SPI_CLK<br>SYSCSSPICLK || ? || Connected to [[Syscon Hardware|Syscon]] pin 82 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]]), or pin 61 ([[Template:Syscon_pinout_LQFP_100_pins|LQFP 100 pins layout]])
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| | U19 || /SB_SPI_CS<br>/SYSCSSPICS || ? || Connected to [[Syscon Hardware|Syscon]] pin 83 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]]), or pin 35 ([[Template:Syscon_pinout_LQFP_100_pins|LQFP 100 pins layout]])
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| | V19 || SB_SPI_DO<br>SYSCSSPIDI || ? || Connected to [[Syscon Hardware|Syscon]] pin 80 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]]), or pin 59 ([[Template:Syscon_pinout_LQFP_100_pins|LQFP 100 pins layout]])
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| | V22 || SYSCSSPIDO || ? || Connected to [[Syscon Hardware|Syscon]] pin 81 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]]), or pin 60 ([[Template:Syscon_pinout_LQFP_100_pins|LQFP 100 pins layout]])
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| | W21 || ? || ? || Connected to [[Syscon Hardware|Syscon]] pin 46 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]]), or pin 55 ([[Template:Syscon_pinout_LQFP_100_pins|LQFP 100 pins layout]])
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| | W22 || SB_INT<br>SYSCSINT || ? || Connected to [[Syscon Hardware|Syscon]] pin 2 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]]), or pin 3 ([[Template:Syscon_pinout_LQFP_100_pins|LQFP 100 pins layout]])
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| | AA17 || ? || ? || Connected to [[Syscon Hardware|Syscon]] pin 8 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]]), or pin 2 ([[Template:Syscon_pinout_LQFP_100_pins|LQFP 100 pins layout]])
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| | AA18 || ? || ? || Connected to [[Syscon Hardware|Syscon]] pin 7 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]]), or pin 10 ([[Template:Syscon_pinout_LQFP_100_pins|LQFP 100 pins layout]])
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| |}
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| *Southbridge to syscon pads ---> https://i.postimg.cc/XqbcznPr/REX-001-South-Bridge-pad-layout-copy.jpg
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| {{Wikify}}
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| {{Motherboard Components}}<noinclude>[[Category:Main]]</noinclude> | | {{Motherboard Components}}<noinclude>[[Category:Main]]</noinclude> |
