CXD9208GP: Difference between revisions

Revision as of 16:32, 4 October 2022

Sony CXD9208GP (PS2 bridge chip)

bridge chip from EE+GS to the CXM4024R

6-710-433-01 / IC7301
Used on PS3 FAT CECHAxx/COK-001 and CECHBxx/COK-001
Unknown bridge chip from EE+GS to the CXM4024R (see MultiAV) and the RSX

Pinout

14x14 pads array


Pad	Name		Description
	Internal	External
A1	TEST_IN_0	GND	Ground
A2	PLLAVS1	GND	Ground
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14

B1
B2
B3	PLLAVD1	+1.5V_BRIDGE
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14

C1
C2
C3	TEST_IN_1	GND	Ground
C4	VSS2	GND	Ground
C5	VSS2	GND	Ground
C6
C7
C8
C9
C10
C11	VSS	GND	Ground
C12	VSS	GND	Ground
C13
C14

D1
D2
D3
D4	VSS	GND	Ground
D5	VDDC	+1.5V_BRIDGE
D6	VDD	+1.5V_EEGS_VDDO
D7	VSS	GND	Ground
D8	VDDC	+1.5V_BRIDGE
D9	VDD	+1.5V_EEGS_VDDO
D10	VSS	GND	Ground
D11	VDD	+1.5V_EEGS_VDDO
D12
D13
D14

E1
E2
E3
E4	VSS2	GND	Ground
E5	VDDS	+3.3V_BRIDGE
E6	VDDC	+1.5V_BRIDGE
E7	VDD	+1.5V_EEGS_VDDO
E8	VSS2	GND	Ground
E9	TEST_IN_3	GND	Ground
E10	VDD2	+1.5V_EEGS_VDDO
E11	VDD2	+1.5V_EEGS_VDDO
E12	TEST_IN_4	GND	Ground
E13
E14

F1
F2
F3
F4	VDDC	+1.5V_BRIDGE
F5	VDDS	+3.3V_BRIDGE
F6	VSS	GND	Ground
F7	VSS	GND	Ground
F8	TEST_IN_2	GND	Ground
F9	VDDS	+3.3V_BRIDGE
F10	VDD	+1.5V_EEGS_VDDO
F11	VSS2	GND	Ground
F12
F13
F14

G1
G2
G3
G4	VSS	GND	Ground
G5	VSS2	GND	Ground
G6	VSS	GND	Ground
G7	VDDS	+3.3V_BRIDGE
G8	VDD2	+1.5V_EEGS_VDDO
G9	VDDC	+1.5V_BRIDGE
G10	VSS2	GND	Ground
G11	VDDC	+1.5V_BRIDGE
G12
G13
G14

H1
H2
H3
H4	VDDC	+1.5V_BRIDGE
H5	TEST_PLL_BP_0	GND	Ground
H6	VSS2	GND	Ground
H7	VDDC	+1.5V_BRIDGE
H8	VDDS	+3.3V_BRIDGE
H9	VDD2	+1.5V_EEGS_VDDO
H10	VSS	GND	Ground
H11	VDD	+1.5V_EEGS_VDDO
H12
H13
H14

J1
J2
J3
J4	VDDC	+1.5V_BRIDGE
J5	VDDS	+3.3V_BRIDGE
J6	VSS	GND	Ground
J7	VDDS	+3.3V_BRIDGE
J8	VSS	GND	Ground
J9	VSS	GND	Ground
J10	VSS2	GND	Ground
J11	VDDC	+1.5V_BRIDGE
J12
J13
J14

K1
K2
K3
K4	VSS	GND	Ground
K5	VDDC	+1.5V_BRIDGE
K6	VDDS	+3.3V_BRIDGE
K7	VDDS	+3.3V_BRIDGE
K8	TEST_PLL_BP_1	GND	Ground
K9	VSS	GND	Ground
K10	VDD	+1.5V_EEGS_VDDO
K11	VSS	GND	Ground
K12
K13
K14

L1
L2
L3
L4	VDDC	+1.5V_BRIDGE
L5	VSS2	GND	Ground
L6	VSS	GND	Ground
L7	VSS2	GND	Ground
L8	VSS	GND	Ground
L9	VDDS	+3.3V_BRIDGE
L10	VDDS	+3.3V_BRIDGE
L11	VSS	GND	Ground
L12
L13
L14

M1
M2
M3
M4	VSS2	GND	Ground
M5
M6
M7
M8
M9
M10
M11	SW1.5	SW1.5	Connected to Syscon pad UNK (BGA 200 pads layout) ?
M12
M13	VBLK	EEGS_VBLK1	Connected to EEGS ? (Vertical BLanK, control signal ?)
M14	HBLK	EEGS_HBLK1	Connected to EEGS ? (Horizontal BLanK, control signal ?)

N1
N2
N3	PLLAVD0	+1.5V_BRIDGE
N4
N5
N6
N7
N8
N9	SW2.65	SW2.65	Connected to Syscon pad UNK (BGA 200 pads layout) ?
N10	SW3.3	SW3.3	Connected to Syscon pad UNK (BGA 200 pads layout) ?
N11	SW1.81	SW1.81	Connected to Syscon pad UNK (BGA 200 pads layout) ?
N12
N13	PCLKEN	PCLKEN
N14	EGRST	EGRST	Connected to Syscon pad UNK (BGA 200 pads layout) ?. It seems this line is shared with EEGS, both are reset together

P1
P2	PLLAVS0	GND	Ground
P3
P4
P5
P6
P7
P8
P9	SW1.8	SW1.8	Connected to Syscon pad UNK (BGA 200 pads layout) ?
P10	SW2.5	SW2.5	Connected to Syscon pad UNK (BGA 200 pads layout) ?
P11	SW1.2	SW1.2	Connected to Syscon pad UNK (BGA 200 pads layout) ?
P12	SW3.1	SW3.1	Connected to Syscon pad UNK (BGA 200 pads layout) ?
P13
P14	PWRUP_EE	PWRUP_EE	Connected to Syscon pad UNK (BGA 200 pads layout) ?. It seems this line is shared with EEGS, both are powered up together

@@ Line 370: / Line 370: @@
 | data-sort-value="M12" | M12 ||  ||  ||  ||
 |-
-| data-sort-value="M13" | M13 || {{cellcolors|#aaf}} VBLK || EEGS_VBLK1 || {{pino}} || Connected to EEGS ? ('''V'''ertical '''BL'''ac'''K''', control signal ?)
+| data-sort-value="M13" | M13 || {{cellcolors|#aaf}} VBLK || EEGS_VBLK1 || {{pino}} || Connected to EEGS ? ('''V'''ertical '''BL'''an'''K''', control signal ?)
 |-
-| data-sort-value="M14" | M14 || {{cellcolors|#aaf}} HBLK || EEGS_HBLK1 || {{pino}} || Connected to EEGS ? ('''H'''orizontal '''BL'''ac'''K''', control signal ?)
+| data-sort-value="M14" | M14 || {{cellcolors|#aaf}} HBLK || EEGS_HBLK1 || {{pino}} || Connected to EEGS ? ('''H'''orizontal '''BL'''an'''K''', control signal ?)
 |-
 ! data-sort-value="M99" style="line-height:2em; border-right:hidden" | &nbsp; || data-sort-value="ZZZ" style="border-left:hidden; border-right:hidden" | &nbsp; || data-sort-value="ZZZ" style="border-left:hidden; border-right:hidden" | &nbsp; || data-sort-value="ZZZ" style="border-left:hidden; border-right:hidden" | &nbsp; || data-sort-value="ZZZ" style="border-left:hidden" | &nbsp;

CXD9208GP: Difference between revisions

Revision as of 16:32, 4 October 2022

Sony CXD9208GP (PS2 bridge chip)

Pinout

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