CXD9208GP: Difference between revisions

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(→‎Pinout: A disabled TEST port, and 2 ground lines of a PLL port)
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! style="border-top:hidden; padding:0px; background-position:50%" | !! style="width:25px; min-width:25px; padding-right:0px" | Internal !! style="width:25px; min-width:25px; padding-right:0px" | External !! style="border-top:hidden; background-position:50%" | !! style="border-top:hidden; background-position:50%" |  
! style="border-top:hidden; padding:0px; background-position:50%" | !! style="width:25px; min-width:25px; padding-right:0px" | Internal !! style="width:25px; min-width:25px; padding-right:0px" | External !! style="border-top:hidden; background-position:50%" | !! style="border-top:hidden; background-position:50%" |  
|-
|-
| data-sort-value="A01" | A1 || || || ||  
| data-sort-value="A01" | A1 || {{cellcolors|#333|#fff}} TEST_IN_0 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="A02" | A2 || || || ||  
| data-sort-value="A02" | A2 || {{cellcolors|#333|#fff}} PLLAVS1 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="A03" | A3 ||  ||  ||  ||  
| data-sort-value="A03" | A3 ||  ||  ||  ||  
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| data-sort-value="C02" | C2 ||  ||  ||  ||  
| data-sort-value="C02" | C2 ||  ||  ||  ||  
|-
|-
| data-sort-value="C03" | C3 || || || ||  
| data-sort-value="C03" | C3 || {{cellcolors|#333|#fff}} TEST_IN_1 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="C04" | C4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="C04" | C4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
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| data-sort-value="E08" | E8 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E08" | E8 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="E09" | E9 || || || ||  
| data-sort-value="E09" | E9 || {{cellcolors|#333|#fff}} TEST_IN_3 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="E10" | E10 ||  ||  ||  ||  
| data-sort-value="E10" | E10 ||  ||  ||  ||  
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| data-sort-value="E11" | E11 ||  ||  ||  ||  
| data-sort-value="E11" | E11 ||  ||  ||  ||  
|-
|-
| data-sort-value="E12" | E12 || || || ||  
| data-sort-value="E12" | E12 || {{cellcolors|#333|#fff}} TEST_IN_4 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="E13" | E13 ||  ||  ||  ||  
| data-sort-value="E13" | E13 ||  ||  ||  ||  
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| data-sort-value="F07" | F7 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="F07" | F7 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="F08" | F8 || || || ||  
| data-sort-value="F08" | F8 || {{cellcolors|#333|#fff}} TEST_IN_2 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="F09" | F9 ||  ||  ||  ||  
| data-sort-value="F09" | F9 ||  ||  ||  ||  
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| data-sort-value="H04" | H4 ||  ||  ||  ||  
| data-sort-value="H04" | H4 ||  ||  ||  ||  
|-
|-
| data-sort-value="H05" | H5 || || || ||  
| data-sort-value="H05" | H5 || {{cellcolors|#333|#fff}} TEST_PLL_BP_0 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="H06" | H6 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="H06" | H6 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
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| data-sort-value="K07" | K7 ||  ||  ||  ||  
| data-sort-value="K07" | K7 ||  ||  ||  ||  
|-
|-
| data-sort-value="K08" | K8 || || || ||  
| data-sort-value="K08" | K8 || {{cellcolors|#333|#fff}} TEST_PLL_BP_1 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="K09" | K9 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="K09" | K9 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
Line 408: Line 408:
| data-sort-value="P01" | P1 ||  ||  ||  ||  
| data-sort-value="P01" | P1 ||  ||  ||  ||  
|-
|-
| data-sort-value="P02" | P2 || || || ||  
| data-sort-value="P02" | P2 || {{cellcolors|#333|#fff}} PLLAVS0 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="P03" | P3 ||  ||  ||  ||  
| data-sort-value="P03" | P3 ||  ||  ||  ||  

Revision as of 14:30, 4 October 2022

Sony CXD9208GP (PS2 bridge chip)

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bridge chip from EE+GS to the CXM4024R

6-710-433-01 / IC7301
Used on PS3 FAT CECHAxx/COK-001 and CECHBxx/COK-001
Unknown bridge chip from EE+GS to the CXM4024R (see MultiAV) and the RSX

Pinout

14x14 pads array

Pad Name Type Description
Internal External
A1 TEST_IN_0 GND
Others
 Ground
A2 PLLAVS1 GND
Others
 Ground
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
         
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
         
C1
C2
C3 TEST_IN_1 GND
Others
 Ground
C4 VSS2 GND
Others
 Ground
C5 VSS2 GND
Others
 Ground
C6
C7
C8
C9
C10
C11 VSS GND
Others
 Ground
C12 VSS GND
Others
 Ground
C13
C14
         
D1
D2
D3
D4 VSS GND
Others
 Ground
D5
D6
D7 VSS GND
Others
 Ground
D8
D9
D10 VSS GND
Others
 Ground
D11
D12
D13
D14
         
E1
E2
E3
E4 VSS2 GND
Others
 Ground
E5
E6
E7
E8 VSS2 GND
Others
 Ground
E9 TEST_IN_3 GND
Others
 Ground
E10
E11
E12 TEST_IN_4 GND
Others
 Ground
E13
E14
         
F1
F2
F3
F4
F5
F6 VSS GND
Others
 Ground
F7 VSS GND
Others
 Ground
F8 TEST_IN_2 GND
Others
 Ground
F9
F10
F11 VSS2 GND
Others
 Ground
F12
F13
F14
         
G1
G2
G3
G4 VSS GND
Others
 Ground
G5 VSS2 GND
Others
 Ground
G6 VSS GND
Others
 Ground
G7
G8
G9
G10 VSS2 GND
Others
 Ground
G11
G12
G13
G14
         
H1
H2
H3
H4
H5 TEST_PLL_BP_0 GND
Others
 Ground
H6 VSS2 GND
Others
 Ground
H7
H8
H9
H10 VSS GND
Others
 Ground
H11
H12
H13
H14
         
J1
J2
J3
J4
J5
J6 VSS GND
Others
 Ground
J7
J8 VSS GND
Others
 Ground
J9 VSS GND
Others
 Ground
J10 VSS2 GND
Others
 Ground
J11
J12
J13
J14
         
K1
K2
K3
K4 VSS GND
Others
 Ground
K5
K6
K7
K8 TEST_PLL_BP_1 GND
Others
 Ground
K9 VSS GND
Others
 Ground
K10
K11 VSS GND
Others
 Ground
K12
K13
K14
         
L1
L2
L3
L4
L5 VSS2 GND
Others
 Ground
L6 VSS GND
Others
 Ground
L7 VSS2 GND
Others
 Ground
L8 VSS GND
Others
 Ground
L9
L10
L11 VSS GND
Others
 Ground
L12
L13
L14
         
M1
M2
M3
M4 VSS2 GND
Others
 Ground
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
         
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
         
P1
P2 PLLAVS0 GND
Others
 Ground
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14 PWRUP_EE
In
Syscon
CXR713F Series
CELL
90 nm
65 nm
45 nm
RSX
90 nm
65 nm
40 nm
28 nm
CELL RAM
(XDR)
Elpida
Qimonda
Samsung
RSX RAM
(GDDR3 or 5)
Elpida
Infineon & Qimonda
Samsung
Hynix
PS2
Compatibility
EEGS
RDRAM
Bridge
South Bridge
Starship2
Flash
NAND
Samsung
NOR
Macronix
Samsung
Spansion
eMMC
Samsung
Panasonic
BD SATA/PATA
BD Controllers
On BD board
Sony
Renesas SCEI
Integrated
Sony
Renesas SCEI
Others
IDT SCEI
Wireless
Connectors
Other
Diverse Comp.
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