XDR Configuration: Difference between revisions
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{{Reverse engineering}}<noinclude>[[Category:Main]]</noinclude> | From DECR-1000 | ||
<pre> | |||
0000h: 04 02 10 20 08 00 00 01 80 00 FF C0 32 00 06 11 | |||
0010h: 01 70 7C FE 48 20 00 00 01 E0 62 84 05 5A D6 B0 | |||
0020h: 5D 70 71 80 02 10 00 00 0A 96 3D 60 E1 C0 C8 00 | |||
0030h: 00 00 00 00 00 00 00 00 ED D6 12 29 59 4B A6 B4 | |||
0040h: 53 49 AC B6 88 C4 62 20 00 00 00 00 00 40 00 00 | |||
0050h: 08 A0 0C A0 14 79 18 79 00 58 00 80 00 01 FC 01 | |||
0060h: 00 06 00 0F FC 0A 00 06 00 0F 37 00 00 3F 23 28 | |||
0070h: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF | |||
</pre> | |||
=Structure= | |||
{| class="wikitable FCK__ShowTableBorders" | |||
|- | |||
!Offset!!Size!!Description | |||
|- | |||
|0x0||1||Amount of chip per channel | |||
|- | |||
|0x1||1||Density of the chip? | |||
0x2 = 64MiB? | |||
0x4 = 128MiB? | |||
|- | |||
|0x2||1||Native bus width of the chip? | |||
0x10 = x16? | |||
0x20 = x32? | |||
|- | |||
|0x3||1||Bus width per channel? (Always 0x20?) | |||
|- | |||
|} | |||
{{Reverse engineering}}<noinclude> | |||
[[Category:Main]] | |||
</noinclude> | |||
Revision as of 17:49, 19 July 2024
The XDR configuration is sent to the Cell BE processor via syscon's packet during booting, however you can query it at any moment.
To fetch it you need to send a packet to the system controller with service id = 0x12 and payload consisting of two zero bytes, an answer have a size of 0x84 bytes (status and data).
It contains some register values which are used during initialization of memory interface controller at startup.
Sample
Here are example outputs from Slim consoles (only data):
0000h: 02 02 10 20 08 00 00 01 80 00 FF C0 32 00 06 11 ... ........2... 0010h: 01 70 7C FE 50 20 00 00 00 E0 62 84 05 5A D6 B0 .p|.P ....b..Z.. 0020h: 5D 70 71 80 02 10 00 00 0A 96 3D 60 E1 C0 C8 00 ]pq.......=`.... 0030h: 00 00 00 00 00 00 00 00 ED D6 12 29 59 4B A6 B4 ...........)YK.. 0040h: 53 49 AC B6 88 C4 62 20 00 00 00 00 00 40 00 00 SI....b .....@.. 0050h: 08 54 0C 54 14 9F 18 9F 00 58 00 80 00 01 FC 01 .T.T.....X...... 0060h: 00 06 00 0F FC 0A 00 06 00 0F 37 00 00 10 23 28 ..........7...#( 0070h: 20 00 80 FF FF FF FF FF FF FF FF FF FF FF FF FF ...............
0000h: 01 04 20 20 08 00 00 01 80 00 FF C0 32 00 06 11 .. ........2... 0010h: 01 70 7C FE 60 40 00 00 00 E0 62 84 05 5A D6 B0 .p|.`@....b..Z.. 0020h: 5D 70 71 80 02 10 00 00 0A 96 3D 60 E1 C0 C8 00 ]pq.......=`.... 0030h: 00 00 00 00 00 00 00 00 ED D6 12 29 59 4B A6 B4 ...........)YK.. 0040h: 53 49 AC B6 88 C4 62 20 00 00 00 00 00 40 00 00 SI....b .....@.. 0050h: 08 54 0C 54 14 C6 18 C6 00 58 00 80 00 01 FC 01 .T.T.....X...... 0060h: 00 06 00 0F FC 0A 00 06 00 0F 37 00 00 10 23 28 ..........7...#( 0070h: 2D 00 80 FF FF FF FF FF FF FF FF FF FF FF FF FF -...............
From DECR-1000
0000h: 04 02 10 20 08 00 00 01 80 00 FF C0 32 00 06 11 0010h: 01 70 7C FE 48 20 00 00 01 E0 62 84 05 5A D6 B0 0020h: 5D 70 71 80 02 10 00 00 0A 96 3D 60 E1 C0 C8 00 0030h: 00 00 00 00 00 00 00 00 ED D6 12 29 59 4B A6 B4 0040h: 53 49 AC B6 88 C4 62 20 00 00 00 00 00 40 00 00 0050h: 08 A0 0C A0 14 79 18 79 00 58 00 80 00 01 FC 01 0060h: 00 06 00 0F FC 0A 00 06 00 0F 37 00 00 3F 23 28 0070h: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
Structure
| Offset | Size | Description |
|---|---|---|
| 0x0 | 1 | Amount of chip per channel |
| 0x1 | 1 | Density of the chip?
0x2 = 64MiB? 0x4 = 128MiB? |
| 0x2 | 1 | Native bus width of the chip?
0x10 = x16? 0x20 = x32? |
| 0x3 | 1 | Bus width per channel? (Always 0x20?) |
