Southbridge: Difference between revisions
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PS4 southbridge contains two processors named EMC and EAP that are mainly used on boot, during rest mode and for servicing. | PS4 southbridge contains two processors named EMC and EAP on the same die that are mainly used on boot, during rest mode and for servicing. | ||
= Southbridge processors = | = Components = | ||
== Southbridge processors == | |||
The two processors are on the same die. It is a SoC (System on Chip). | |||
== EMC == | === EMC === | ||
EMC could stand for External Micro Controller. EMC was named MediaCon by some people when its name was still unknown. | EMC could stand for External Micro Controller. EMC was named MediaCon by some people when its name was still unknown. | ||
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The role of EMC is to load EMC IPL and EAP kernel, to be an interface for icc for the main [[APU]] kernel and [[Syscon]] and to offer a debug interface via UART that does not rely on [[Syscon]] or main APU. EMC runs its own FreeBSD kernel. It is a Marvell Armada, an ARM-based SoC. Sony stuck a [[PCIe]] bridge on it. It exposes ARM peripherals to the x86 side. There is some extra stuff (e.g. HPET, ACPI stuff). | The role of EMC is to load EMC IPL and EAP kernel, to be an interface for icc for the main [[APU]] kernel and [[Syscon]] and to offer a debug interface via UART that does not rely on [[Syscon]] or main APU. EMC runs its own FreeBSD kernel. It is a Marvell Armada, an ARM-based SoC. Sony stuck a [[PCIe]] bridge on it. It exposes ARM peripherals to the x86 side. There is some extra stuff (e.g. HPET, ACPI stuff). | ||
EMC cpuid = 412FC231 (ARM Cortex-M3 r2p1) | EMC cpuid = 412FC231 (ARM Cortex-M3 r2p1). CPU clock: maybe about 100MHz. | ||
== EAP == | === EAP === | ||
EAP could stand for External Application Processor. | EAP could stand for External Application Processor. | ||
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The role of EAP is to handle media (online [[Wireless]]/[[GbLAN]], [[Bluray Drive]] and [[Harddrive]]) even in standby mode. EAP runs its own FreeBSD kernel in standby mode, activated to handle tasks such as downloading updates while the PS4 is in standby. | The role of EAP is to handle media (online [[Wireless]]/[[GbLAN]], [[Bluray Drive]] and [[Harddrive]]) even in standby mode. EAP runs its own FreeBSD kernel in standby mode, activated to handle tasks such as downloading updates while the PS4 is in standby. | ||
= | EAP consists of Marvell PJ4C B0 rev 1 cores, ARMv7 CORTEX-A8 running FreeBSD 9 kernel. CPU clock: 500MHz. DDR clock: 800MHz. | ||
As EAP Core software is unsigned, unencrypted and easily replaceable on PS4 HDD with a PS4 kernel exploit, it is possible to run homebrew code on EAP processor. See [https://github.com/psxdev/eapdev eapdev by Bigboss (psxdev)]. | |||
== Auxiliary components == | |||
The Southbridge is connected to the main [[APU]] by [ | The Southbridge is connected to the main [[APU]] by [[PCIe PCI_Express x4]] and to [[Syscon]] by SPI. | ||
It handles several tasks to offload the main processor/[[APU]]: | It handles several tasks to offload the main processor/[[APU]]: | ||
* Network connections | * Network connections: [[Wireless]] and [[GbLAN]], including background downloading and [[PlayGo]] | ||
* File handling ([[Bluray Drive]], [[Harddrive]] and [[USB 3.0]]), including background caching | * File handling ([[Bluray Drive]], [[Harddrive]] and [[USB 3.0]]), including background caching | ||
* Main serial flash handling | * Main serial flash handling | ||
[[Aeolia]] chip is connected to its own 256MB (or 2GB???) DDR3 SDRAM ("sbram" as for SouthBridge RAM) Samsung [[K4B2G1646E-BCK0]], the main serial flash [[MX25L25635FMI-10G]], SATA bridge [[MB86C311B]], [[GbLAN]] controller [[88EC060-NN82]], etc. See also [[:File:PS4_-_SAA-001_diagram.png]] | |||
= Southbridge revisions = | = Southbridge revisions = |
Revision as of 00:19, 26 February 2021
PS4 southbridge contains two processors named EMC and EAP on the same die that are mainly used on boot, during rest mode and for servicing.
Components
Southbridge processors
The two processors are on the same die. It is a SoC (System on Chip).
EMC
EMC could stand for External Micro Controller. EMC was named MediaCon by some people when its name was still unknown.
The role of EMC is to load EMC IPL and EAP kernel, to be an interface for icc for the main APU kernel and Syscon and to offer a debug interface via UART that does not rely on Syscon or main APU. EMC runs its own FreeBSD kernel. It is a Marvell Armada, an ARM-based SoC. Sony stuck a PCIe bridge on it. It exposes ARM peripherals to the x86 side. There is some extra stuff (e.g. HPET, ACPI stuff).
EMC cpuid = 412FC231 (ARM Cortex-M3 r2p1). CPU clock: maybe about 100MHz.
EAP
EAP could stand for External Application Processor.
The role of EAP is to handle media (online Wireless/GbLAN, Bluray Drive and Harddrive) even in standby mode. EAP runs its own FreeBSD kernel in standby mode, activated to handle tasks such as downloading updates while the PS4 is in standby.
EAP consists of Marvell PJ4C B0 rev 1 cores, ARMv7 CORTEX-A8 running FreeBSD 9 kernel. CPU clock: 500MHz. DDR clock: 800MHz.
As EAP Core software is unsigned, unencrypted and easily replaceable on PS4 HDD with a PS4 kernel exploit, it is possible to run homebrew code on EAP processor. See eapdev by Bigboss (psxdev).
Auxiliary components
The Southbridge is connected to the main APU by PCIe PCI_Express x4 and to Syscon by SPI.
It handles several tasks to offload the main processor/APU:
- Network connections: Wireless and GbLAN, including background downloading and PlayGo
- File handling (Bluray Drive, Harddrive and USB 3.0), including background caching
- Main serial flash handling
Aeolia chip is connected to its own 256MB (or 2GB???) DDR3 SDRAM ("sbram" as for SouthBridge RAM) Samsung K4B2G1646E-BCK0, the main serial flash MX25L25635FMI-10G, SATA bridge MB86C311B, GbLAN controller 88EC060-NN82, etc. See also File:PS4_-_SAA-001_diagram.png
Southbridge revisions
There are three major hardware revisions, named Aeolia, Belize and Baikal.
See also Aeolia.
Southbridge revisions per chassis
Model (chassis) | Motherboards | Southbridge Codename | Southbridge Labeling |
---|---|---|---|
D1000 | All CVN | Aeolia | CXD90025G |
1000 | All SAA | Aeolia | CXD90025G |
1100 | All SAB | Aeolia | CXD90025G |
1200 | All SAC | Belize | CXD90036G |
2000 | All SAD | Belize | CXD90036G |
D7000 | All HAC | Belize | CXD90036G |
2100 | Some SAE | Belize 2 | CXD90046GG |
7000 | All NVA | Belize 2 | CXD90046GG |
2200 | Some SAE, all SAF | Baikal | CXD90042GG |
7100 | All NVB | Baikal | CXD90042GG |
7200 | All NVG | Baikal | CXD90042GG |
Motherboards per southbridge revisions
Southbridge Codename | Southbridge Labeling | Motherboards |
---|---|---|
Aeolia | CXD90025G |
CVN-K12 |
Belize | CXD90036G |
HAC-001 |
Belize 2 | CXD90046GG |
NVA-001 |
Baikal | CXD90042GG |
NVB-004 |
|