Talk:Syscon Hardware: Difference between revisions

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m (this speculation was incorrect, pin1 is at bottom-left corner, indicated by a mark (a dot of copper color) in the motehrboard, as can be seen in Media:Syscon_SW2-303_Unsoldered.JPG)
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== Problem with syscon pinout numeration in wiki in the SWX-xxx series (128 pins package) ==
In all the SWX-xxx series pages the pinout is numered starting with the pin1 at bottom-left corner (when viewing the syscon in the same orientation than the printed texts) this way:
*"""pin 1 left bottom at mark, counter clockwise from south (pins 1-38) to east (pins 39-64), north (pins 65-102), west (103-128))"""
In the first SW series is barelly visible (in the photos it looks is not marked) but in newer series is more visible, and is located at bottom-rigth corner, see this photos i marked:
http://666kb.com/i/cnj3qic8k412x3p8r.jpg
*All photos are taken from wiki visibles in his respective pages... look for the original photo to see it in better resolution (when posible because there are not much photos of syscons in wiki or internet)
If this is correct, is needed to change the info about the pinout in all the affected pinout tables (in all SWX-xxx pages)
== PowerON/off HDMI/CEC, WiFi, Bluetooth, GbLAN, buttons etc ==
== PowerON/off HDMI/CEC, WiFi, Bluetooth, GbLAN, buttons etc ==
There is no seperate communication processor on the PS3. Powering is handled by syscon.
There is no seperate communication processor on the PS3. Powering is handled by syscon.

Revision as of 12:02, 18 April 2021

PowerON/off HDMI/CEC, WiFi, Bluetooth, GbLAN, buttons etc

There is no seperate communication processor on the PS3. Powering is handled by syscon.

  • Power and eject buttons/switchs are connected with syscon (indirectly), there is no protocol involved, the syscon pins related with this buttons has 2 posible states: 3.3v (when button is not pressed)... or 0v (when button is pressed)

Multipage Correction

<TizzyT> eussnl my syscon is CXR714120-301GB its different form what the wiki says
CECHH / DIA-001

Package

http://pastie.org/private/tkcfjwit37huzyzoie7z5g BGA

ball count: 4x16 + 8x14 + 2x12 = 64+112+24 = 200 pads

new QF package is 26 * 38 = 128 pins

Clocks

SysCon clocks: 

T4 XTAL / T5 EXTAL goes to [X4001] of 16.9344 MHz
C16 OSCIN / B16 OSCOUT goes to [X4002] of 32.768 kHz

http://oi52.tinypic.com/2s9ziw0.jpg

Backup Mode / Diag

BACKUP_MODE / DIAG_MODE pins on Gen 2 might be pins 110 and 111. They are pulled low. Not completely sure, but looking at those pins in relation to what's around them seems like it could be those two.

SEM-001 CECHG 

Pink is N15 BACKUP_MODE
Blue is N16 DIAG_MODE

picture: http://psx-scene.com/forums/attachments/f149/26456d1300550098-brick-recovery-research-untitled-1.jpg source: http://psx-scene.com/forums/780185-post344.html !unverified!

According to schematics, DIAG and BACKUP_MODE are are shown in the following picture for COK-001 and COK-002 Motherboards - http://goput.it/69k.jpg These pins are tied to 3.3v so grounding them should enable each mode respectively. !unverified! - DIAG mode has been verified to work - a seperate grounding of the P16 pin on the SYSCON

SoftID

Note: moved from seperate page, as there are already over 8 different syscon pages and the very same info is mention in depth on the SC firmware and SC hardware page (and in 150 wiki edits on the sysinfo page :/) we dont have a sperate page for every SELF flag either ;) (although there are >4 pages describing SELF :/)

a SoftID is just a 0x4 code that tells you the hardware revision of the syscon.
This info can be get through the More System Information method.
You can find them also inside the SYS_CON_FIRMWARE_*********.pkg (Syscon_Firmware) at the offset 0x28E (In this link you can found the list of the Syscon update packages)
every SoftID is associated with the ps3 mainboard. this means that you can know if a SC is compatible with your board without opening a PS3 ( Syscon Hardware)

SoftID SC Generation notes
Phats
0B8E 1 -
0C16 2 COK-002
0D52 3 -
0DBF 4 -
0E69 5 -
0F29 6 -
0F38 7 -
065D 8 -
Slims
0832 9 -
08C2 10 -
0918 11 -

Datasheet of SoC similar to syscon

COK-002 with 0DBF syscon

Information: https://lh5.googleusercontent.com/-UiaHRjhdt50/UesKSGuxdFI/AAAAAAAAGOU/0FV8Fazyl60/s800/TV2013072019053700.jpg

Min ver: https://lh5.googleusercontent.com/-iUOuidm6v3g/UexEQily6TI/AAAAAAAAGOk/zSfBMpYDRAM/s800/TV2013072117272000.jpg

Board type: https://lh6.googleusercontent.com/-K1sc66WzJxo/Ue1Mdr5mHeI/AAAAAAAAGO8/rnqlidQAVfY/s800/DSC01591.JPG

Syscon: https://lh6.googleusercontent.com/-OTxjx3qJV0M/Ue1L2itOfRI/AAAAAAAAGO0/Bv6zli_xQQg/s800/DSC01590.JPG


Talk

-This breaks lot of standards/pages/tables in wiki, can you add some notes please ?. E.g: the board came from official repair service, bought in a normal shop, or is a frankenstein made at home ?, it boots correctly and allows firmware updates ?. If it works normally i think this proves CXR713120-20xGB and CXR714120-30xGB shares the same pinout, but the fact that is using 0DBF SoftID is a bit shocking (maybe because is the minimal SoftID allowed by CXR714120-30xGB ?... check SoftID examples in this table) --Sandungas 22:07, 24 July 2013 (MSK)

-The console is a CECHE01 MG (Metal Gear Solid 4 edition) and came with a 3rd generation BD drive (the first type with 2 lens). It had never been to SONY for service. It works normally, correctly and as you could see, has a minimum version which is compatible with the motherboard type. --l_oliveira


SHA1 hashes stored at eeprom

from http://www.edepot.com/playstation3.html

"Files finally stored into the FLASH regions have their associated SHA-1 hash value stored in the SYSCON EEPROM for authentication and verification purposes. "

What happens if we change those hashes to something a 3.55 ofw would have? (assuming we were doing this experiment on a hackable console?)

PS2 Mechacon vs PSP Syscon vs PS3 Syscon vs PSVita Syscon vs PS4 Syscon

Production Start Date (<=) PS2 Mechacon PSP Syscon PS3 Syscon PSVita Syscon PS4 Syscon Used IC/CPU Core
10/1999 CXP101064 - - - - Sony SPC970 (100 pin)
01/2000 CXP102064 - - - -
09/2000 CXP103049 - - - - Sony SPC??? (136 pin)
08/2004 - BARxx - - - NEC D780032AY (78K0/78003xA, 64 pin)
07/2005 - B30x - - - NEC D78F0531 (78K0/KE2 V2.00, 64 pin)
07/2007 - B40x / 40xx - - - NEC D78F0544 (78K0/KF2 V2.00, 84 pin)
07/2008 - 3xxx - - - NEC D78F0534 (78K0/KE2 V2.00, 64 pin)
03/2003 CXR706080 - - - - Sony SR11 (ARM7TDMI)
PS2 (Dragon): 164 pin
PS3 (Donkey): 200 pin
09/2004 CXR716080 - CXR713120 - -
07/2007 CXR726080 - CXR714120 - -
03/2008 - - SW - - NEC D78F11AA (78K0R/KH3 V3.40, 128 pin)
05/2009 - - SW2 - - NEC D78F11BB (78K0R/KH3 V1.00, 128 pin)
07/2010 - - - "SC" - NEC D79F0109 (78K0R/KH3-L V1.00, 121 pin)
06/2011 - - SW3 - - NEC D78F11CC (78K0R/KG3 V1.00, 100 pin)
07/2013 - - - - C0L Renesas R5F100PL (RL78/G13 V3.03, 100 pin)
08/2013 - - - A0xxx - Renesas R5F1ZCRK (RL78/G13 V3.03, 121 pin)
04/2015 - - - - C0L2 Renesas R5F101LL (RL78/G13 V3.03, 64 pin)
  • The SPC900 core was designed by Texas Instruments ([1])
  • CXP101064, CXP102064 are similar to CXP97 (CXP971000, CXP972032, CXP973064, CXP973F064), the CXP103049 matches no COTS because of its OCD support
    • In-Circuit-Emulator: Mitek NICE-SPC970 ([2]); Debug software: SVD970; Flash programmer: SFP-2
  • A F inside the model name specifies that the IC contains flash memory.
    • Mass-produced CXR/SW units don't have/use program flash memory for updates, instead an encrypted firmware patch is stored on the data-"EEPROM"
  • CXR7 series uses Sony SR11 CPU (ARM7TDMI)
    • Models with public datasheet: CXR702080, CXR702F080, CXR704060
  • Prototype PS3 Syscon's:
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