Service Connectors: Difference between revisions

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JTAG/UART/SPI/Diagnostic I/O used in Sony repair centers if a PS4 couldn't be fixed by software.  
JTAG/UART/SPI/Diagnostic I/O used in Sony repair centers if a PS4 could not be fixed by software.  
 
== Preproduction Generation ==
 
=== Syscon ===


==Preproduction Generation==
<div style="float:right">[[File:CVN-001-ServConn.png|200px|thumb|left|[[DUH-D1000xA_series]][[CVN-001]] img1]]<br/> </div>
<div style="float:right">[[File:CVN-001-ServConn.png|200px|thumb|left|[[DUH-D1000xA_series]][[CVN-001]] img1]]<br/> </div>
[[A00-C0L]]
 
[[A00-COL]]
 
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|-
|-
| 32 ||  ||  
| 32 ||  ||  
|-
|}
|}
=== Southbridge ===
See [[Aeolia]].


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|-
|-
| 20 || ||  
| 20 || ||  
|}
=== PCIe ===
[[PCIe]] [[CVN-001]]
<div style="float:right">[[File:PCI-Service_Connectors.png|200px|thumb|left|[[DUH-D1000xA_series]][[CVN-001]] img1]]<br/> </div>
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"
|- bgcolor="#cccccc"
! Pin !! Name !! Description
|-
| 1 ||  ||
|-
| 2 ||  ||
|-
| 3 ||  ||
|-
| 4 ||  ||
|-
| 5 ||  ||
|-
| 6 ||  ||
|-
| 7 ||  ||
|-
| 8 ||  ||
|-
| 9 ||  ||
|-
| 10 ||  ||
|-
| 11 ||  ||
|-
| 12 ||  ||
|-
| 13 ||  ||
|-
| 14 ||  ||
|-
| 15 ||  ||
|-
|-
|}<br /><br />
| 16 ||  ||
|-
| 17 ||  ||
|-
| 18 ||  ||
|-
| 19 ||  ||
|-
| 20 ||  ||
|}


==1st Generation==
<div style="float:right">[[File:CUH-10xxA - SAA-001 - 30 pins port - img1.jpg|200px|thumb|left|[[CUH-10xxA]] [[SAA-001]] pads3/30 pins - img1]]<br />[[File:CUH-10xxA - SAA-001 - 30 pins port - img2.jpg|200px|thumb|left|[[CUH-10xxA]] [[SAA-001]] pads3/30 pins - img2]]</div>
[[A01-C0L]]
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| 5 ||  ||  
| 5 ||  ||  
|-
|-
| 6 || Gnd || Internal ground
| 6 || ||  
|-
|-
| 7 || I2C || I2C bus (100 kHz clock)
| 7 || ||  
|-
|-
| 8 || Gnd || Internal ground
| 8 || ||  
|-
|-
| 9 ||  ||  
| 9 ||  ||  
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| 12 ||  ||  
| 12 ||  ||  
|-
|-
| 13 || Gnd || Internal ground
| 13 || ||  
|-
|-
| 14 ||  ||  
| 14 ||  ||  
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| 16 ||  ||  
| 16 ||  ||  
|-
|-
| 17 || Gnd || Internal ground
| 17 || ||  
|-
|-
| 18 ||  ||  
| 18 ||  ||  
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|-
|-
| 20 ||  ||  
| 20 ||  ||  
|}
== First Generation ==
=== Syscon ===
<div style="float:right">[[File:CUH-10xxA - SAA-001 - 30 pins port - img1.jpg|200px|thumb|left|[[CUH-10xxA]] [[SAA-001]] pads3/30 pins - img1]]<br />[[File:CUH-10xxA - SAA-001 - 30 pins port - img2.jpg|200px|thumb|left|[[CUH-10xxA]] [[SAA-001]] pads3/30 pins - img2]]</div>
See [[A01-COL]].
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"
|- bgcolor="#cccccc"
! Pin !! Name !! Description
|-
| 1 || VCC? ||
|-
| 2 || NC || No connection
|-
| 3 ||  || == pin 1
|-
| 4 ||  ||
|-
|-
| 21 || ||  
| 5 ||  ||
|-
| 6 || Gnd || Internal ground
|-
| 7 || I2C || I2C bus (100 kHz clock) -> HDR-D pin 2
|-
| 8 ||  || -> HDR-D pin 1
|-
| 9 || Gnd || Internal ground
|-
| 10 || SC-P70 ||
|-
| 11 ||  ||
|-
| 12 || SC-P72 ||
|-
| 13 || ||
|-
| 14 || Gnd || Internal ground
|-
| 15 || SC-P12 ||
|-
| 16 || SC-P11 ||
|-
| 17 || SC-P51 ||
|-
| 18 || Gnd || Internal ground
|-
| 19 || -> SB? ||
|-
| 20 || -> SB? ||
|-
| 21 || -> SB? ||  
|-
|-
| 22 || Gnd || Internal ground
| 22 || SC-P40 (TOOL0) open circuit ||
|-
|-
| 23 || ||  
| 23 || Gnd || Internal ground
|-
|-
| 24 || ||  
| 24 || SC-RESET# ||  
|-
|-
| 25 || Gnd || Internal ground
| 25 || GND|| Internal ground
|-
|-
| 26 ||  ||  
| 26 ||  ||  
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| 27 ||  ||  
| 27 ||  ||  
|-
|-
| 28 ||  ||  
| 28 || SC-P122 ||
|-
| 29 || SC-P121 ||
|-
| 30 || NC || No connection
|}
 
=== Southbridge ===
 
<div style="float:right">[[File:CUH-10xxA - SAA-001 - 20 pins port - img1.jpg|200px|thumb|left|[[CUH-10xxA]] [[SAA-001]] pads2/20 pins - img1]]<br />[[File:CUH-10xxA - SAA-001 - 20 pins port - img2.jpg|200px|thumb|left|[[CUH-10xxA]] [[SAA-001]] pads2/20 pins - img2]]</div>
 
See [[Aeolia]], [[Southbridge]] debug.
 
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"
|- bgcolor="#cccccc"
! Pin !! Name !! Description
|-
| 1 || VCC?  ||
|-
| 2 || Gnd || Internal ground
|-
| 3 ||  ||
|-
| 4 || Gnd || Internal ground
|-
| 5 ||  ||
|-
| 6 ||  ||
|-
| 7 ||  ||
|-
| 8 || Gnd || Internal ground
|-
| 9 ||  ||
|-
| 10 ||
|-
| 11 || Gnd || Internal ground
|-
| 12 || SB-20/S (SDIO?)  || probably for eMMC
|-
| 13 || Gnd || Internal ground
|-
| 14 || SB-19/R (SDIO?) ||
|-
| 15 || SB SDIO? ||
|-
| 16 || SB SDIO? ||
|-
| 17 || SB SDIO? ||
|-
| 18 || SB SDIO? ||  
|-
|-
| 29 || ||  
| 19 || Gnd || Internal ground
|-
|-
| 30 || ||  
| 20 || NC ||
|-
|-
|}
|}


==2nd Generation==
== Second Generation ==


* TODO
* TODO

Latest revision as of 00:29, 2 February 2022

JTAG/UART/SPI/Diagnostic I/O used in Sony repair centers if a PS4 could not be fixed by software.

Preproduction Generation[edit | edit source]

Syscon[edit | edit source]

DUH-D1000xA_seriesCVN-001 img1

A00-COL

Pin Name Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Southbridge[edit | edit source]

See Aeolia.

Pin Name Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PCIe[edit | edit source]

PCIe CVN-001

DUH-D1000xA_seriesCVN-001 img1

Pin Name Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

First Generation[edit | edit source]

Syscon[edit | edit source]

CUH-10xxA SAA-001 pads3/30 pins - img1

CUH-10xxA SAA-001 pads3/30 pins - img2

See A01-COL.

Pin Name Description
1 VCC?
2 NC No connection
3 == pin 1
4
5
6 Gnd Internal ground
7 I2C I2C bus (100 kHz clock) -> HDR-D pin 2
8 -> HDR-D pin 1
9 Gnd Internal ground
10 SC-P70
11
12 SC-P72
13
14 Gnd Internal ground
15 SC-P12
16 SC-P11
17 SC-P51
18 Gnd Internal ground
19 -> SB?
20 -> SB?
21 -> SB?
22 SC-P40 (TOOL0) open circuit
23 Gnd Internal ground
24 SC-RESET#
25 GND Internal ground
26
27
28 SC-P122
29 SC-P121
30 NC No connection

Southbridge[edit | edit source]

CUH-10xxA SAA-001 pads2/20 pins - img1

CUH-10xxA SAA-001 pads2/20 pins - img2

See Aeolia, Southbridge debug.

Pin Name Description
1 VCC?
2 Gnd Internal ground
3
4 Gnd Internal ground
5
6
7
8 Gnd Internal ground
9
10
11 Gnd Internal ground
12 SB-20/S (SDIO?) probably for eMMC
13 Gnd Internal ground
14 SB-19/R (SDIO?)
15 SB SDIO?
16 SB SDIO?
17 SB SDIO?
18 SB SDIO?
19 Gnd Internal ground
20 NC

Second Generation[edit | edit source]

  • TODO
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