Template:CELL pad layout 65nm: Difference between revisions

Revision as of 04:01, 10 November 2022

CELL 65nm pad layout (CELL view)
Pad A1 at top-left corner

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CELL pad layout 65nm
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Pad	Name		Description
	Internal	External
AV13	SPI_SI	BE_SPI_DO	Connected to Syscon pad N2 (BGA 200 pads layout), or pin 80 (LQFP 128 pins layout)
AV23	THERMAL_OVERLOAD	SYS_THR_ALRT	Connected to Syscon pad E9(BGA 200 pads layout), or pin UNK (LQFP 128 pins layout) through transistor
AW13	SPI_EN	BE_SPI_CS	Connected to Syscon pad M2 (BGA 200 pads layout), or pin 83 (LQFP 128 pins layout)
AW18	HARD_RESET	BE_RESET_AND	Connected to Syscon pad P2 (BGA 200 pads layout), or pin UNK (LQFP 128 pins layout)
AY13	SPI_CLK	BE_SPI_CLK	Connected to Syscon pad N1 (BGA 200 pads layout), or pin 82 (LQFP 128 pins layout)
BA13	SPI_SO	BE_SPI_DI	Connected to Syscon pad M1 (BGA 200 pads layout), or pin 81 (LQFP 128 pins layout) through 47 resistor
BA17	ATTENTION	BE_INT	Connected to Syscon pad T2 (BGA 200 pads layout), or pin 3 (LQFP 128 pins layout)
BA19	POWER_GOOD	BE_POWGOOD	Connected to Syscon pad P1 (BGA 200 pads layout), or pin UNK (LQFP 128 pins layout)
AV29	STI_THERMAL[0]		Connected to CELL temperature monitor pin 2 (D+)
AU29	STI_THERMAL[1]		Connected to CELL temperature monitor pin 3 (D-)
C15	STI_THERMAL2[0]		Not connected
B14	STI_THERMAL2[1]		Not connected

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 ! style="border-bottom:hidden; padding:2px" | Pad !! colspan="2" | Name !! style="border-bottom:hidden; padding:2px" | Type !! style="border-bottom:hidden" | Description