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Tachyon is the codename of the PSP main CPU SoC IC. It is a Sony custom-made LSI which holds the main CPU (Allegrex), the VFPU coprocessor, the Media Engine CPU and its embedded DRAM, the Graphics Engine, the AVC decoder, the Virtual Mobile Engine DSP, the [[Kirk]] and [[Spock]] crypto engines, and the 4KB embedded mask ROM which holds the [[iplloader]] and routines to boot into service mode. Tachyon has one primary CPU core which is responsible for running the XMB and games, and a second CPU core (Media Engine) which implements the audio and video decoding functionality of the PSP.
[[File:PSP CXD2962GG.jpg|thumb|PSP CXD2962GG]]


[[File:PSP CXD2962GG.jpg|thumb|left|PSP CXD2962GG]]<br>
<b>Tachyon</b> is the codename of the PSP main CPU SoC IC. It is a Sony custom-made LSI which holds the main CPU (Allegrex), the VFPU coprocessor, the Media Engine CPU and its embedded DRAM, the Graphics Engine, the AVC decoder, the Virtual Mobile Engine DSP, the [[Kirk]] and [[Spock]] crypto engines, and the 4KB embedded mask ROM which holds the [[iplloader]] and routines to boot into service mode.
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Tachyon has one primary CPU core which is responsible for running the [[XMB]] and games, and a second CPU core (<i>[[Media Engine]]</i>) which implements the audio and video decoding functionality of the PSP.
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== Main Core "SC" ==
== Main Core "SC" ==


The PSP's CPU is a dual core 32-bit Little Endian MIPS based on the R4000 design with a few custom instructions.
See [[Allegrex]].


Both CPU cores have their own 16 KiB Instruction and 16KiB Data caches. The main CPU has an internal 16 KiB of scratchpad RAM that is accessed directly without going through the system bus.
== Media Engine ==


The main CPU has three coprocessors:
See [[Media Engine]].
*COP0 - general system control
*COP1 - 32-bit Floating Point Unit
*COP2 - Vector Floating Point Unit (up to 3.2 GFLOPS)


The CPU defaults to 222MHz, but can be configured to run from 1-333 MHz.
== Virtual Mobile Engine ==


The CPU cores are connected to main memory and other peripherals like the Graphics Engine through a system bus that is limited to 1/2 of the CPU's configured clock speed.
See [[Virtual Mobile Engine]].


== Media Engine ==
== Graphics Engine ==
 
: <i>See main article: <b>[[Graphics]]</b></i>
 
== Memory mapping ==
 
This memory mapping is shared by the SC, the GE & the ME, except the VRAM which is accessible only by the SC and the GE.


The Media Engine ("ME") is a second MIPS based CPU core that was not directly accessible by licensed developers. Instead, Sony runs code on the ME to facilitate decoding audio and video assets, along with the help of more specialized hardware like the Virtual Mobile Engine and "AVC".
{| class="wikitable"
|-
! Start !! End !! Size !! Description
|-
| 0x00010000 || 0x00013FFF || 0x00004000 (<i>16KiB</i>) || Allegrex Scratchpad
|-
| 0x04000000 || 0x041FFFFF || 0x00200000 (<i>2MiB</i>)  || Graphics Engine VRAM
|-
| 0x08000000 || 0x087FFFFF || 0x00800000 (<i>8MiB</i>)  || Allegrex Kernel memory (RAM)
|-
| 0x08800000 || 0x09FFFFFF || 0x01800000 (<i>24MiB</i>) || Allegrex User memory (RAM)
|-
| 0x1C000000 || ?          || ?                        || Hardware registers
|-
| 0x1FC00000 || 0x1FDFFFFF || 0x00200000                || MIPS Reset Vector
|-
| 0x1FE00000 || ?          || ?                        || Hardware registers
|-
|}


The ME runs at the same clock frequency as the main CPU core.
See [[Hardware Registers]] for details about the hardware registers.


The ME has two co-processors:
Access can be cached & privileged or not by changing the first 4 bits (<i>31-28 bits</i>) of the address using this virtual memory mapping:
*COP0 - general system control
{| class="wikitable"
*COP1 - 32-bit Floating Point Unit
|-
! Address !! Name !! Is it cached? !! Permission || Description
|-
| 0x<b>0</b>0000000 || KU0  || Cached  || User/Supervisor/Kernel || Main memory
|-
| 0x<b>4</b>0000000 || KU1  || Uncached || User/Supervisor/Kernel || Often used for VRAM
|-
| 0x<b>8</b>0000000 || K0    || Cached  || Kernel || Main kernel memory
|-
| 0x<b>A</b>0000000 || K1    || Uncached || Kernel || Mainly used for hardware registers
|-
| 0x<b>C</b>0000000 || K2/KS || Cached  || Supervisor/Kernel || Usage unknown/unconfirmed
|-
| 0x<b>E</b>0000000 || K3    || Cached  || Kernel || Usage unknown/unconfirmed
|-
|}


== Graphics Engine ==
== PSP-1000 VFPU bug ==


== Virtual Mobile Engine ==
PSP-1000 CPU has broken <code>ulv.q</code> instruction, that causes FPU registers corruption.


The VME appears to be one half of Sony's "Virtual Mobile Engine Concept 2" where a CPU would take care of "lightweight control tasks" and reconfigurable hardware logic (the VME) would do all of the "heavy work in a power efficient manner". See [https://www.yumpu.com/en/document/read/10961029/virtual-mobile-enginetm-vme-sony Virtual Mobile Engine - LSI that "Changes its Spots"].
You can see more about it [https://sites.google.com/a/davidgf.es/davidgf-net/home/psp-dev/vfpu-test?tmpl=%2Fsystem%2Fapp%2Ftemplates%2Fprint%2F here].


== Versions ==  
== Versions ==  
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* https://www.zdnet.com/article/sony-reveals-some-specs-for-psp-handheld/ (2004)
* https://www.zdnet.com/article/sony-reveals-some-specs-for-psp-handheld/ (2004)


https://www.extremetech.com/extreme/56942-sony-details-psp-chip-specs
* https://www.extremetech.com/extreme/56942-sony-details-psp-chip-specs


https://www.copetti.org/writings/consoles/playstation-portable/
* https://www.copetti.org/writings/consoles/playstation-portable/

Latest revision as of 21:32, 17 June 2024

PSP CXD2962GG

Tachyon is the codename of the PSP main CPU SoC IC. It is a Sony custom-made LSI which holds the main CPU (Allegrex), the VFPU coprocessor, the Media Engine CPU and its embedded DRAM, the Graphics Engine, the AVC decoder, the Virtual Mobile Engine DSP, the Kirk and Spock crypto engines, and the 4KB embedded mask ROM which holds the iplloader and routines to boot into service mode.

Tachyon has one primary CPU core which is responsible for running the XMB and games, and a second CPU core (Media Engine) which implements the audio and video decoding functionality of the PSP.

Main Core "SC"[edit | edit source]

See Allegrex.

Media Engine[edit | edit source]

See Media Engine.

Virtual Mobile Engine[edit | edit source]

See Virtual Mobile Engine.

Graphics Engine[edit | edit source]

See main article: Graphics

Memory mapping[edit | edit source]

This memory mapping is shared by the SC, the GE & the ME, except the VRAM which is accessible only by the SC and the GE.

Start End Size Description
0x00010000 0x00013FFF 0x00004000 (16KiB) Allegrex Scratchpad
0x04000000 0x041FFFFF 0x00200000 (2MiB) Graphics Engine VRAM
0x08000000 0x087FFFFF 0x00800000 (8MiB) Allegrex Kernel memory (RAM)
0x08800000 0x09FFFFFF 0x01800000 (24MiB) Allegrex User memory (RAM)
0x1C000000 ? ? Hardware registers
0x1FC00000 0x1FDFFFFF 0x00200000 MIPS Reset Vector
0x1FE00000 ? ? Hardware registers

See Hardware Registers for details about the hardware registers.

Access can be cached & privileged or not by changing the first 4 bits (31-28 bits) of the address using this virtual memory mapping:

Address Name Is it cached? Permission Description
0x00000000 KU0 Cached User/Supervisor/Kernel Main memory
0x40000000 KU1 Uncached User/Supervisor/Kernel Often used for VRAM
0x80000000 K0 Cached Kernel Main kernel memory
0xA0000000 K1 Uncached Kernel Mainly used for hardware registers
0xC0000000 K2/KS Cached Supervisor/Kernel Usage unknown/unconfirmed
0xE0000000 K3 Cached Kernel Usage unknown/unconfirmed

PSP-1000 VFPU bug[edit | edit source]

PSP-1000 CPU has broken ulv.q instruction, that causes FPU registers corruption.

You can see more about it here.

Versions[edit | edit source]

PSP-1000[edit | edit source]

  • CPU and DDR are discrete ICs on the motherboard
  • 32 MiB main memory (DDR)
  • 2 MiB Media Engine memory (eDRAM)

PSP-2000 and later[edit | edit source]

  • DDR is brought into the CPU's package
  • 64 MiB main memory (DDR)
  • 4 MiB Media Engine memory (eDRAM)

See also[edit | edit source]

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