Tachyon

PSP CXD2962GG

Tachyon is the codename of the PSP main CPU SoC IC. It is a Sony custom-made LSI which holds the main CPU (Allegrex), the VFPU coprocessor, the Media Engine CPU and its embedded DRAM, the Graphics Engine, the AVC decoder, the Virtual Mobile Engine DSP, the Kirk and Spock crypto engines, and the 4KB embedded mask ROM which holds the iplloader and routines to boot into service mode.

Tachyon has one primary CPU core which is responsible for running the XMB and games, and a second CPU core (Media Engine) which implements the audio and video decoding functionality of the PSP.

Main Core "SC"

The PSP's CPU, named Allegrex — is a dual core 32-bit Little Endian MIPS processor, based on the R4000 design with a few custom instructions.

Both CPU cores have their own 16 KiB Instruction and 16 KiB Data caches. The main CPU has an internal 16 KiB of scratchpad RAM, that is accessed directly without going through the system bus.

The main CPU has three coprocessors:

• COP0: general system control
• COP1: 32-bit Floating Point Unit
• COP2: Vector Floating Point Unit (up to 3.2 GFLOPS)

It has some instructions from MIPS IV: ext, ins, wsbw, seb, seh, rotr, rot(r)v, bitrev, clz, clo.

It doesn't seem to have:

• 64-bit instructions (of course)
• ll, ldc1, ldc2, lwc2, sc, sdc1, sdc2, swc2 (some of them are actually replaced by VFPU instructions with different names)
• T* (trap and TLB) instructions
• bltzal, bgezal, bltzall, bgezall
• COP2 (VFPU) branching instructions

It also has its own instructions:

• halt (opcode 0x70000000): This instructions waits for an interruption to wake it up.
• mfic (opcode 0x70000024 with mask 0xFFFF07FF): It retrieves the interrupt controller state (1: interruptions enabled, 0: interruptions disabled) into the register described by mask 0x0000F800.
• mtic (opcode 0x70000026 with mask 0xFFFF07FF): It sets the interrupt controller state to the value which is in the register described by mask 0x0000F800.

The CPU defaults to 222 MHz, but can be configured to run from 1-333 MHz.

The CPU cores are connected to main memory and other peripherals like the Graphics Engine through a system bus, that is limited to half of the CPU's configured clock speed.

Since the PSP doesn't have a MMU, the COP0 registers related to TLBs are unused. The PSP also uses the obscure instructions cfc0/ctc0 to access "control registers" which are used by the PSP firmware to store various low level data.

Calling convention

The PSP calling convention seems a bit non-standard:

• Arguments are passed through following registers: $a0, $a1, $a2, $a3, $t0, $t1, $t2, $t3, then on the stack
• Registers $s0, $s1, $s2, $s3, $s4, $s5, $s6, $s7, $fp (used as a normal registers), $ra (return address), $sp (stack pointer) are saved (or restored) by the callee
• Registers $t4, $t5, $t6, $t7, $t8, $t9 are temporary registers, not saved by the callee
• Registers $v0, $v1 contain the return value of a function: $v0 for the lower 32-bits and $v1 for the higher 32-bits (if appliable)

Some registers are used only by the kernel:

• $gp and $k0 are used in only a few specific places in the kernel
• $k1 is used to check permissions: each time an user function is called, it shifts $k1 left by 11 bits. The function is in user mode if the $k1 value has then its first (highest value) bit set. In then checks either if a pointer has its higher bit set, and/or if its end has its higher bit set, and/or if its size has its higher bit set. If one of those bits is set and we're in user mode, the function returns an error (if it checked the pointer/buffer, which is not always the case).
• $at (assembly temporary) is used as a temporary register, for hardware manipulation sometimes (to store the hardware register address when reading/writing from/to it).

Media Engine

The Media Engine (or shortly ME) — is a second MIPS based CPU core, that was not directly accessible by licensed developers. Instead, Sony runs code on the ME to facilitate decoding audio and video assets, along with the help of more specialized hardware like the Virtual Mobile Engine and "AVC".

The ME runs at the same clock frequency as the main CPU core. It seems to have the same instruction set.

The ME has two co-processors:

• COP0: general system control
• COP1: 32-bit Floating Point Unit

It has three instructions the main CPU doesn't have (or used):

• DBREAK (also present on other MIPS processors): used only once in the ME firmware
• MTVME
• MFVME

These two last instructions actually have the same opcodes as LDL and SDL, which this CPU doesn't have. The instructions are actually encoded like this:

 ldl $reg, off($a3) <=> mfvme $reg, $off
 sdl $reg, off($a3) <=> mtvme $reg, $off

They might be used to store and retrieve information from and to the VME. They seem to be only used for video decoding.

Graphics Engine

See main article: Graphics

Virtual Mobile Engine

The VME appears to be one half of Sony's "Virtual Mobile Engine Concept 2" where a CPU would take care of "lightweight control tasks" and reconfigurable hardware logic (the VME) would do all of the "heavy work in a power efficient manner". See Virtual Mobile Engine - LSI that "Changes its Spots".

It might be something like a reconfigurable DSP; noone has been able to interpret its "firmware" yet.

It can be accessed from the ME through the mfvme/mtvme instructions or through DMA with addresses from 0x440F8000 to 0x44100000 (excluded).

Memory mapping

This memory mapping is shared by the SC, the GE & the ME, except the VRAM which is accessible only by the SC and the GE.

Start	End	Size	Description
0x00010000	0x00013FFF	0x00004000 (16KiB)	Allegrex Scratchpad
0x04000000	0x041FFFFF	0x00200000 (2MiB)	Graphics Engine VRAM
0x08000000	0x087FFFFF	0x00800000 (8MiB)	Allegrex Kernel memory (RAM)
0x08800000	0x097FFFFF	0x01800000 (24MiB)	Allegrex User memory (RAM)
0x1C000000	?	?	Hardware registers
0x1FC00000	0x1FDFFFFF	0x00200000	MIPS Reset Vector
0x1FE00000	?	?	Hardware registers

See Hardware Registers for details about the hardware registers.

Access can be cached & privileged or not by changing the first 4 bits (31-28 bits) of the address using this virtual memory mapping:

Address	Name	Is it cached?	Permission	Description
0x00000000	KU0	Cached	User/Supervisor/Kernel	Main memory
0x40000000	KU1	Uncached	User/Supervisor/Kernel	Often used for VRAM
0x80000000	K0	Cached	Kernel	Main kernel memory
0xA0000000	K1	Uncached	Kernel	Mainly used for hardware registers
0xC0000000	K2/KS	Cached	Supervisor/Kernel	Usage unknown/unconfirmed
0xE0000000	K3	Cached	Kernel	Usage unknown/unconfirmed

Versions

PSP-1000

• CPU and DDR are discrete ICs on the motherboard
• 32 MiB main memory (DDR)
• 2 MiB Media Engine memory (eDRAM)

PSP-2000 and later

• DDR is brought into the CPU's package
• 64 MiB main memory (DDR)
• 4 MiB Media Engine memory (eDRAM)

See also

• https://www.zdnet.com/article/sony-reveals-some-specs-for-psp-handheld/ (2004)

• https://www.extremetech.com/extreme/56942-sony-details-psp-chip-specs

• https://www.copetti.org/writings/consoles/playstation-portable/