KLMAG2GE4A-A001: Difference between revisions
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* [http://www.jedec.org/sites/default/files/Victor_Tsai.pdf Victor_Tsai.pdf] | * [http://www.jedec.org/sites/default/files/Victor_Tsai.pdf Victor_Tsai.pdf] | ||
* [http://www.freescale.com/files/training_pdf/WBNR_FTF10_NET_F0598_PDF.pdf WBNR_FTF10_NET_F0598_PDF.pdf] | * [http://www.freescale.com/files/training_pdf/WBNR_FTF10_NET_F0598_PDF.pdf WBNR_FTF10_NET_F0598_PDF.pdf] | ||
See also : http://www.vitadevwiki.com/index.php?title=Media | |||
<br /><br /><br /><br /><br /><br /><br /> | <br /><br /><br /><br /><br /><br /><br /> | ||
Revision as of 02:47, 14 February 2013
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Samsung KLMAG2GE4A-A001
Used in 'Super Slim 12GB' CECH-4003A MPX-001 accompanied by Panasonic MN66840
eMMC MLC NAND
FBGA169
Handy PDFs:
- Embedded MMC (eMMC) Standard MMCA 4.4 (JESD84-A44)(March 2009)
- iNAND_e_MMC_4_41_IF_data_sheet_v1_0.pdf
- JESD84-A44.pdf
- Victor_Tsai.pdf
- WBNR_FTF10_NET_F0598_PDF.pdf
See also : http://www.vitadevwiki.com/index.php?title=Media
Testpoints eMMC
| eMMC Testpoint |
Pad # | Name | Type | Description |
|---|---|---|---|---|
| - | A-G 1-14 | - | NP or NC | not present or not connected |
| H3 | DAT0 | I/O | Data I/O : Bidirectional channel used for data transfer | |
| H4 | DAT1 | I/O | Data I/O : Bidirectional channel used for data transfer | |
| H5 | DAT2 | I/O | Data I/O : Bidirectional channel used for data transfer | |
| J2 | DAT3 | I/O | Data I/O : Bidirectional channel used for data transfer | |
| J3 | DAT4 | I/O | Data I/O : Bidirectional channel used for data transfer | |
| J4 | DAT5 | I/O | Data I/O : Bidirectional channel used for data transfer | |
| J5 | DAT6 | I/O | Data I/O : Bidirectional channel used for data transfer | |
| J6 | DAT7 | I/O | Data I/O : Bidirectional channel used for data transfer | |
| K2 | VDDi | Internal power node. Connect 0.1uF capacitor from VDDi to ground. | ||
| K4 | VSSQ | Ground | Memory controller core and MMC IF ground connection | |
| K6 | VSSQ | Supply | Memory controller core and MMC IF I/O power supply | |
| M6 | VCC | Supply | Flash I/O and memory power supply | |
| M7 | VSS | Ground | Flash I/O and memory ground connection | |
| N5 | VCC | Supply | Flash I/O and memory power supply | |
| P5 | VSS | Ground | Flash I/O and memory ground connection | |
| R10 | VSS | Ground | Flash I/O and memory ground connection | |
| T10 | VCC | Supply | Flash I/O and memory power supply | |
| U5 | RESET | Hardware Reset | ||
| U8 | VSS | Ground | Flash I/O and memory ground connection | |
| U9 | VCC | Supply | Flash I/O and memory power supply | |
| W4 | VCCQ | Supply | Memory controller core and MMC IF I/O power supply | |
| W5 | CMD | I/O | Command: A bidirectional channel used for device initialisation and command transfers | |
| W6 | CLK | Input | Clock: Each cycle directs a 1-bit transfer on the command and DAT lines | |
| Y2 | VSSQ | Ground | Memory controller core and MMC IF ground connection | |
| Y4 | VCCQ | Supply | Memory controller core and MMC IF I/O power supply | |
| Y5 | VSSQ | Ground | Memory controller core and MMC IF ground connection | |
| AA3 | VCCQ | Supply | Memory controller core and MMC IF I/O power supply | |
| AA4 | VSSQ | Ground | Memory controller core and MMC IF ground connection | |
| AA5 | VCCQ | Supply | Memory controller core and MMC IF I/O power supply | |
| AA6 | VSSQ | Ground | Memory controller core and MMC IF ground connection | |
| AB-HG 1-14 | - | NP or NC | not present or not connected |
remark: the following Pad #letter's are not used: I, O, Q, S, X, Z, AI, AO, AQ, AS, AX, AZ