Template:Elpida memory product code: Difference between revisions

Latest revision as of 13:48, 11 February 2023

Elpida memory product code
[edit]
Product Family	Density	Organization	Power Supply, Interface	Die Rev.	Package	Speed	Internal Code (optional)	Enviroment Code
X: XDR DRAM W: GDDR5 SDRAM	51: 512M 10: 1Gb 11: ?	16: x16bit 32: x32bit	A: 1.8V, DRSL B: 1.5V +/- 0.075V, DRSL	A: Rev1 B: Rev2 C: Rev3 D: Rev4	SE: FBGA BG: FBGA	3C: 3.2Gbps (tRAC = 35ns, C Bin) 4D: 4.0Gbps (tRAC = 34ns, D Bin) 28: ?	A2: ?	E: Lead Free F: Lead & Halogen Free

@@ Line 1: / Line 1: @@
-{| class="wikitable" style="margin:auto"
+{| class="wikitable" style="font-size:small; margin:auto"
-|+Elpida XDR DRAM part number decoder {{ed right|Elpida XDR DRAM part number decoder}}
+|+Elpida memory product code {{ed right|Elpida memory product code}}
-! Product Family !! Density !! Organization !! Power Supply, Interface !! Die Rev. !! Package !! Speed !! Internal Code !! Enviroment Code
+! Product Family !! Density !! Organization !! Power Supply, Interface !! Die Rev. !! Package !! Speed !! Internal Code<br>(<abbr title="Some products doesnt includes this code">optional</abbr>) !! Enviroment Code
 |-
-| '''X''': XDR DRAM
+| '''X''': XDR DRAM<br>'''W''': GDDR5 SDRAM
-| '''51''': 512M<br />'''10''': 1Gb
+| '''51''': 512M<br />'''10''': 1Gb<br>'''11''': ?
 | '''16''': x16bit<br />'''32''': x32bit
 | '''A''': 1.8V, DRSL<br />'''B''': 1.5V +/- 0.075V, DRSL
 | '''A''': Rev1<br />'''B''': Rev2<br />'''C''': Rev3<br />'''D''': Rev4
-| '''SE''': FBGA<br />'''BG''': FBGA ?
+| '''SE''': FBGA<br />'''BG''': FBGA
-| '''3C''': 3.2Gbps (tRAC = 35ns, C Bin)<br />'''4D''': 4.0Gbps (tRAC = 34ns, D Bin)
+| '''3C''': 3.2Gbps (tRAC = 35ns, C Bin)<br />'''4D''': 4.0Gbps (tRAC = 34ns, D Bin)<br>'''28''': ?
-| '''A2''': unknown
+| '''A2''': ?
 | '''E''': Lead Free<br />'''F''': Lead & Halogen Free
 |-
 |}
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