Template:CELL pad layout 65nm: Difference between revisions

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(Style copyed from the 90nm table)
(Prelude to a come up)
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! style="border-top:hidden; padding:0px; background-position:50%" | !! style="width:25px; min-width:25px; padding-right:0px" | Internal !! style="width:25px; min-width:25px; padding-right:0px" | External !! style="border-top:hidden; background-position:50%" | !! style="border-top:hidden; background-position:50%" |  
! style="border-top:hidden; padding:0px; background-position:50%" | !! style="width:25px; min-width:25px; padding-right:0px" | Internal !! style="width:25px; min-width:25px; padding-right:0px" | External !! style="border-top:hidden; background-position:50%" | !! style="border-top:hidden; background-position:50%" |  
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| AV13 || SPI_SI || BE_SPI_DO || {{pini}} || Connected to [[Syscon Hardware|Syscon]] pad N2 ([[Template:Syscon_pinout_BGA_200_pads|BGA 200 pads layout]]), or pin 80 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]])
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| AV23 || THERMAL_OVERLOAD || SYS_THR_ALRT || {{pino}} || Connected to [[Syscon Hardware|Syscon]] pad E9([[Template:Syscon_pinout_BGA_200_pads|BGA 200 pads layout]]), or pin <abbr title="Unknown>UNK</abbr> ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]]) through transistor
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| AW13 || SPI_EN || BE_SPI_CS || {{pini}} || Connected to [[Syscon Hardware|Syscon]] pad M2 ([[Template:Syscon_pinout_BGA_200_pads|BGA 200 pads layout]]), or pin 83 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]])
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| AW18 || HARD_RESET || BE_RESET_AND || {{pini}} || Connected to [[Syscon Hardware|Syscon]] pad P2 ([[Template:Syscon_pinout_BGA_200_pads|BGA 200 pads layout]]), or pin <abbr title="Unknown>UNK</abbr> ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]])
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| AY13 || SPI_CLK || BE_SPI_CLK || {{pini}} || Connected to [[Syscon Hardware|Syscon]] pad N1 ([[Template:Syscon_pinout_BGA_200_pads|BGA 200 pads layout]]), or pin 82 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]])
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| BA13 || SPI_SO || BE_SPI_DI || {{pino}} || Connected to [[Syscon Hardware|Syscon]] pad M1 ([[Template:Syscon_pinout_BGA_200_pads|BGA 200 pads layout]]), or pin 81 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]]) through 47 resistor
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| BA17 || ATTENTION || BE_INT || {{pino}} || Connected to [[Syscon Hardware|Syscon]] pad T2 ([[Template:Syscon_pinout_BGA_200_pads|BGA 200 pads layout]]), or pin 3 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]])
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| BA19 || POWER_GOOD || BE_POWGOOD || {{pini}} || Connected to [[Syscon Hardware|Syscon]] pad P1 ([[Template:Syscon_pinout_BGA_200_pads|BGA 200 pads layout]]), or pin <abbr title="Unknown>UNK</abbr> ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]])
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| AV29 || STI_THERMAL[0] ||  || {{pino}} || Connected to CELL temperature monitor pin 2 (D+)
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| AU29 || STI_THERMAL[1] ||  || {{pino}} || Connected to CELL temperature monitor pin 3 (D-)
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| C15 || STI_THERMAL2[0] ||  || {{pinnc}} || Not connected
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| B14 || STI_THERMAL2[1] ||  || {{pinnc}} || Not connected
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<noinclude>[[Category:Templates]]</noinclude>
<noinclude>[[Category:Templates]]</noinclude>

Revision as of 08:09, 10 November 2022

CELL 65nm pad layout (CELL view)
Pad A1 at top-left corner
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CELL pad layout 65nm
Pad Name Type Description
Internal External