Template:Elpida memory product code: Difference between revisions
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m (Sandungas moved page Template:Elpida XDR DRAM part number decoder to Template:Elpida memory product code without leaving a redirect: more generic name) |
m (this was right, in the datasheets both "SE" and "BG" are simply described as FBGA) |
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| Line 8: | Line 8: | ||
| '''A''': 1.8V, DRSL<br />'''B''': 1.5V +/- 0.075V, DRSL | | '''A''': 1.8V, DRSL<br />'''B''': 1.5V +/- 0.075V, DRSL | ||
| '''A''': Rev1<br />'''B''': Rev2<br />'''C''': Rev3<br />'''D''': Rev4 | | '''A''': Rev1<br />'''B''': Rev2<br />'''C''': Rev3<br />'''D''': Rev4 | ||
| '''SE''': FBGA<br />'''BG''': ? | | '''SE''': FBGA<br />'''BG''': FBGA ? | ||
| '''3C''': 3.2Gbps (tRAC = 35ns, C Bin)<br />'''4D''': 4.0Gbps (tRAC = 34ns, D Bin) | | '''3C''': 3.2Gbps (tRAC = 35ns, C Bin)<br />'''4D''': 4.0Gbps (tRAC = 34ns, D Bin) | ||
| '''A2''': ? | | '''A2''': ? | ||
Revision as of 06:38, 14 April 2021
| Product Family | Density | Organization | Power Supply, Interface | Die Rev. | Package | Speed | Internal Code | Enviroment Code |
|---|---|---|---|---|---|---|---|---|
| X: XDR DRAM | 51: 512M 10: 1Gb |
16: x16bit 32: x32bit |
A: 1.8V, DRSL B: 1.5V +/- 0.075V, DRSL |
A: Rev1 B: Rev2 C: Rev3 D: Rev4 |
SE: FBGA BG: FBGA ? |
3C: 3.2Gbps (tRAC = 35ns, C Bin) 4D: 4.0Gbps (tRAC = 34ns, D Bin) |
A2: ? | E: Lead Free F: Lead & Halogen Free |