Syscon Hardware: Difference between revisions

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Syscon is the main power controller chip. It is responsible for powering up the various power systems and for configuring and initialising the CELL, RSX and southbridge. It communicates with these devices via seperate SPI busses. There is external access by JTAG (Which appears to have been disabled after factory programming) and Serial.
Syscon is the main power controller chip. It is responsible for powering up the various power systems and for configuring and initialising the CELL, RSX and southbridge. It communicates with these devices via seperate SPI busses. There is external access by JTAG (Which appears to have been disabled after factory programming) and Serial.


== Generation 1 ==
[[File:SYSCON_GEN1.JPG|thumb|Syscon 1st Generation (BGA Packaging)]]
[[File:SYSCON_GEN1.JPG|thumb|Syscon 1st Generation (BGA Packaging)]]


BGA Package : 200 Pins
=== Packaging ===


Pin's are labeled in the service manual for this generation
The first generation of the chip comes in a 200 pin BGA package as per below:


<pre>
<pre>
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   T R P N M L K J H G F E D C B A
   T R P N M L K J H G F E D C B A
</pre>
</pre>
=== Pinout ===
Work in progress
{|class="wikitable"
! Pin # !! Name !! Port !! Description
|-
| T2 || /BE_INT || rowspan="9" | Port M <br />Cell Control Line ||
|-
| R1 || PM7 ||
|-
| R2 || PM6 ||
|-
| P1 || BE_POWGOOD ||
|-
| P2 || /BE_RESET ||
|-
| N1 || BE_SPI_CLK || rowspan="4" | Cell SPI Bus
|-
| N2 || BE_SPI_DO
|-
| M1 || BE_SPI_DI
|-
| M2 || /BE_SPI_CS
|-
| L4 || PL8 || rowspan="9" | Port N || rowspan="9" | unused
|-
| L5 || PL7
|-
| K4 || PL6
|-
| K5 || PL5
|-
| J4 || PL4
|-
| J5 || PL3
|-
| H4 || PL2
|-
| H5 || PL1
|-
| H6 || PL0
|-
| A8 || SB_SPI_CLK || rowspan="8" | Port K || rowspan="4" | Southbridge SPI Bus
|-
| B8 || SB_SPI_DO
|-
| A9 || SB_SPI_DI
|-
| B9 || /SB_SPI_CS
|-
| A10 || SEL2_I2C_SCL ||
|-
| B10 || SEL2_I2C_SDA ||
|-
| A11 || ACDC_STBY ||
|-
| B11 || PK0 ||
|}


== Generation 2 ==
== Generation 2 ==

Revision as of 03:23, 8 April 2011

General Information

Syscon is the main power controller chip. It is responsible for powering up the various power systems and for configuring and initialising the CELL, RSX and southbridge. It communicates with these devices via seperate SPI busses. There is external access by JTAG (Which appears to have been disabled after factory programming) and Serial.

Generation 1

Syscon 1st Generation (BGA Packaging)

Packaging

The first generation of the chip comes in a 200 pin BGA package as per below: 

   T R P N M L K J H G F E D C B A
 1 . . . . . . . . . . . . . . . .  1
 2 . . . . . . . . . . . . . . . .  2
 3 . .                         . .  3
 4 . .   . . . . . . . . . .   . .  4
 5 . .   . . . . . . . . . .   . .  5
 6 . .   . . . . . . . . . .   . .  6
 7 . .   . . . . . . . . . .   . .  7
 8 . .   . . . .     . . . .   . .  8
 9 . .   . . . .     . . . .   . .  9
10 . .   . . . . . . . . . .   . . 10
11 . .   . . . . . . . . . .   . . 11
12 . .   . . . . . . . . . .   . . 12
13 . .   . . . . . . . . . .   . . 13
14 . .                         . . 14
15 . . . . . . . . . . . . . . . . 15
16 . . . . . . . . . . . . . . . . 16
   T R P N M L K J H G F E D C B A

Pinout

Work in progress

Pin # Name Port Description
T2 /BE_INT Port M
Cell Control Line
R1 PM7
R2 PM6
P1 BE_POWGOOD
P2 /BE_RESET
N1 BE_SPI_CLK Cell SPI Bus
N2 BE_SPI_DO
M1 BE_SPI_DI
M2 /BE_SPI_CS
L4 PL8 Port N unused
L5 PL7
K4 PL6
K5 PL5
J4 PL4
J5 PL3
H4 PL2
H5 PL1
H6 PL0
A8 SB_SPI_CLK Port K Southbridge SPI Bus
B8 SB_SPI_DO
A9 SB_SPI_DI
B9 /SB_SPI_CS
A10 SEL2_I2C_SCL
B10 SEL2_I2C_SDA
A11 ACDC_STBY
B11 PK0


Generation 2

Syscon 2nd Generation (QFP Packaging)

QFP Package : 128 pins

Currently there is no known pin labelling for this generation

CECHG02 Pinout

Topside Pinout

Syscon Top Pinouts
Pin # Name Description
B3 SW_10 Unknown
A6 MC_RESERVED2 Unknown
E10 MUL_CHKSTP_OUT Unknown
C15 VSS Power Ground
B16 OSCOUT Goes to unpopulated crystal
C16 OSCIN From unpupulated crystal
B15 POW_FAIL Power Failure Signal
H1 PN5 Unknown
H2 PN6 Unknown
R1 PM7 Unknown
R2 PM6 Unknown
M4 SW9 Unknown
M10 XDR_FET_SCK Unknown

Bottomside Pinout

Syscon Bottom Pinouts
Pin # Name Description
R5 VDD +3.3v
R7 DVDD +1.8v
C15 VSS Power Ground
N16 DIAG_MODE Unknown
N15 BACKUP_MODE Unknown
P16 UART0_TxD Serial
P15 UART0_RxD Serial
R9 PQ1 Unknown
B12 POW_SW Power Switch
A12 EJECT_SW Eject Switch
L7 JNTAST JTAG
L8 JRTCK JTAG
L9 JTMS JTAG
K7 JTDI JTAG
K8 JTCK JTAG
K9 JTDO JTAG
M6 SW_7_B Unknown
M8 FANPWM1 Unknown
E5 GX_VSRT Unknown
B5 DVE_RST Unknown
G4 HDMI_RST1 Unknown
D4 XDR_FET_RST Unknown
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