Editing Template:Syscon pinout LQFP 128 pins

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| 16 || 4 || {{cellcolors|#246|#fff}} TO05 || BUZZER || {{pino}} || Connected to the Buzzer through a transistor || 0
| 16 || 4 || {{cellcolors|#246|#fff}} TO05 || BUZZER || {{pino}} || Connected to the Buzzer through a transistor || 0
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| 17 || 4 || {{cellcolors|#33f|#fff}} SO01 ||  || {{pino}} || Connected to [[South Bridge]] [[CXD9963GB]] pad <abbr title="Unknown">UNK</abbr> ? (SB_SPI_DO ?) / [[CELL BE|CELL]] pad AV13 (1308 pads layout, BE_SPI_DO) || 0
| 17 || 4 || {{cellcolors|#33f|#fff}} SO01 ||  || {{pino}} || Connected to [[South Bridge]] [[CXD9963GB]] pad <abbr title="Unknown">UNK</abbr> ? (SB_SPI_DO ?) || 0
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| 18 || 4 || {{cellcolors|#33f|#fff}} SI01 ||  || {{pini}} || Connected to [[South Bridge]] [[CXD9963GB]] pad <abbr title="Unknown">UNK</abbr> ? (SB_SPI_DI ?) / [[CELL BE|CELL]] pad BA13 (1308 pads layout, BE_SPI_DI) || 3v @ standby
| 18 || 4 || {{cellcolors|#33f|#fff}} SI01 ||  || {{pini}} || Connected to [[South Bridge]] [[CXD9963GB]] pad <abbr title="Unknown">UNK</abbr> ? (SB_SPI_DI ?) || 3v @ standby
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| 19 || 4 || {{cellcolors|#33f|#fff}} <span style="text-decoration: overline;">SCK01</span> ||  || {{pino}} || Connected to [[South Bridge]] [[CXD9963GB]] pad <abbr title="Unknown">UNK</abbr> ? (SB_SPI_CLK ?) / [[CELL BE|CELL]] pad AY13 (1308 pads layout, BE_SPI_CLK) || 0
| 19 || 4 || {{cellcolors|#33f|#fff}} <span style="text-decoration: overline;">SCK01</span> ||  || {{pino}} || Connected to [[South Bridge]] [[CXD9963GB]] pad <abbr title="Unknown">UNK</abbr> ? (SB_SPI_CLK ?) || 0
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| 20 || 4 || {{cellcolors|#33f|#fff}} P42 ||  || {{pino}} || Connected to [[South Bridge]] [[CXD9963GB]] pad <abbr title="Unknown">UNK</abbr> ? (SB_SPI_CS ?) / [[CELL BE|CELL]] pad AW13 (1308 pads layout, BE_SPI_CS)|| 0
| 20 || 4 || {{cellcolors|#33f|#fff}} P42 ||  || {{pino}} || Connected to [[South Bridge]] [[CXD9963GB]] pad <abbr title="Unknown">UNK</abbr> ? (SB_SPI_CS ?) || 0
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| 21 || 4 || {{cellcolors|#a74}} TOOL1 || TOOL_CLK || {{pino}} || Connected to [[Service_Connectors#CN.3F.3F.3F.3F|Service Connector 3rd Gen.]] pin 13 (Tool clock) through a missing resistor || 3.0
| 21 || 4 || {{cellcolors|#a74}} TOOL1 || TOOL_CLK || {{pino}} || Connected to [[Service_Connectors#CN.3F.3F.3F.3F|Service Connector 3rd Gen.]] pin 13 (Tool clock) through a missing resistor || 3.0
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| 79 || 1 || {{cellcolors|#a74}} TxD3 || UART0_TxD || {{pino}} || Connected to [[Service_Connectors#CN.3F.3F.3F.3F|Service Connector 3rd Gen.]] pin 10 (UART-TTL terminal Transmit) through a missing resistor<br>Connected to [[PCI]] Connector pin 4 || 3.3
| 79 || 1 || {{cellcolors|#a74}} TxD3 || UART0_TxD || {{pino}} || Connected to [[Service_Connectors#CN.3F.3F.3F.3F|Service Connector 3rd Gen.]] pin 10 (UART-TTL terminal Transmit) through a missing resistor<br>Connected to [[PCI]] Connector pin 4 || 3.3
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| 80 || 1 || {{cellcolors|#33f|#fff}} SO00 || BE_SPI_DO / SB_SPI_DO || {{pino}} || Connected to [[CELL BE|CELL]] pad AV13 (1342 pads layout) / [[South Bridge]] pad V19 [[CXD9963GB]]. Serial Output from Syscon Master to Cell/SB Slave (MOSI) || 0
| 80 || 1 || {{cellcolors|#33f|#fff}} SO00 || BE_SPI_DO || {{pino}} || Connected to [[CELL BE|CELL]] pad AV13 (1342 pads layout), or pad <abbr title="Unknown">UNK</abbr> (1308 pads layout). Serial Output from Syscon Master to Cell Slave (MOSI) || 0
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| 81 || 1 || {{cellcolors|#33f|#fff}} SI00 || BE_SPI_DI / SB_SPI_DI || {{pini}} || Connected to [[CELL BE|CELL]] pad BA13 (1342 pads layout) / [[South Bridge]] pad V22 [[CXD9963GB]]. Serial Input from Cell/SB Slave to Syscon Master (MISO) || 1.2
| 81 || 1 || {{cellcolors|#33f|#fff}} SI00 || BE_SPI_DI || {{pini}} || Connected to [[CELL BE|CELL]] pad BA13 (1342 pads layout), or pad <abbr title="Unknown">UNK</abbr> (1308 pads layout). Serial Input from Cell Slave to Syscon Master (MISO) || 1.2
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| 82 || 1 || {{cellcolors|#33f|#fff}} <span style="text-decoration: overline;">SCK00</span> || BE_SPI_CLK / SB_SPI_CLK || {{pino}} || Connected to [[CELL BE|CELL]] pad AY13 (1342 pads layout) / [[South Bridge]] pad U18 [[CXD9963GB]]. 2.5 Mhz SPI Clock ||
| 82 || 1 || {{cellcolors|#33f|#fff}} <span style="text-decoration: overline;">SCK00</span> || BE_SPI_CLK || {{pino}} || Connected to [[CELL BE|CELL]] pad AY13 (1342 pads layout), or pad <abbr title="Unknown">UNK</abbr> (1308 pads layout). 2.5 Mhz SPI Clock ||
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| 83 || 9 || {{cellcolors|#33f|#fff}} P90 || BE_SPI_CS / SB_SPI_CS|| {{pino}} || Connected to [[CELL BE|CELL]] pad AW13 (1342 pads layout) / [[South Bridge]] pad U19 [[CXD9963GB]]. Chip Select || 2.0
| 83 || 9 || {{cellcolors|#33f|#fff}} P90 || BE_SPI_CS || {{pino}} || Connected to [[CELL BE|CELL]] pad AW13 (1342 pads layout), or pad <abbr title="Unknown">UNK</abbr> (1308 pads layout). Chip Select || 2.0
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| 84 || 9 || P91/EX33 ||  || ? ||  || 3v @ standby
| 84 || 9 || P91/EX33 ||  || ? ||  || 3v @ standby
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