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[[Category:Hardware]] | |||
[[File:SYSCON_GEN1.JPG|thumb|Syscon 1st Generation (BGA Packaging)]] | |||
Syscon is the main power controller chip. It is responsible for powering up the various power systems and for configuring and initialising the [[CELL BE]], [[RSX]] and [[South Bridge]]. It communicates with these devices via seperate SPI busses. There is external access by JTAG (disabled at factory by blowing a fuse), an EEPROM programming interface <!-- not fully examined --> and Serial (UART). The Syscon is a SoC and consists of an ARM7TDMI (ARMv4) CPU, a 256KB EEPROM and 16KB RAM. | |||
= | = Serialnumbers @ SKU = | ||
== Retail == | |||
{| class="wikitable sortable" | |||
== | |||
{| class="wikitable" | |||
|- | |- | ||
! [[ | ! [[SKU Models|Model]] !! [[IDPS|Type]] !! [[Motherboard Revisions|Board]] !! [[Syscon Hardware|Syscon<br />part no.]] !! [[More System Information#First_section|Soft<br />Id.]] !! Notes | ||
| | |||
|- | |- | ||
| [[CECHAxx]] || 0x01 || [[COK-00x#COK-001|COK-001]] || [[CXR713120-201GB]] || 0B8E || | |||
| | |||
| | |||
|- | |- | ||
| [[CECHBxx]] || 0x02 || [[COK-00x#COK-001|COK-001]] || [[CXR713120-201GB]] || 0B8E || | |||
|- | |- | ||
| [[CECHCxx]] || 0x03 || [[COK-00x#COK-002|COK-002]] || [[CXR713120-201GB]] || 0C16 || | |||
|- | |- | ||
| style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHDxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | |||
|- | |- | ||
| | | [[CECHExx]] || 0x04 || [[COK-00x#COK-002|COK-002]]<br /> or<br />[[COK-00x#COK-002W|COK-002W]] || [[CXR713120-201GB]] || 0C16 || | ||
|- | |- | ||
| style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHFxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | |||
|- | |- | ||
| [[CECHGxx]] || 0x05 || [[SEM-00x|SEM-001]] || [[CXR713120-201GB]] || 0D52 || | |||
| | |||
|- | |- | ||
| [[CECHHxx]] || 0x06 || [[DIA-00x#DIA-001|DIA-001]] || [[CXR713120-201GB]] || 0DBF || | |||
| | |||
|- | |- | ||
| style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHIxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | |||
| | |||
|- | |- | ||
| [[CECHJxx]] || 0x07 || [[DIA-00x#DIA-002|DIA-002]] || [[CXR713120-201GB]] || 0E69 || | |||
| | |||
|- | |- | ||
| [[CECHKxx]] || 0x07 || [[DIA-00x#DIA-002|DIA-002]] || [[CXR713120-201GB]] || 0E69 || | |||
| | |||
|- | |- | ||
| [[CECHLxx]] || 0x08 || [[VER-00x|VER-001]] || [[SW-301]]<br /> or<br />[[SW-302]] || 065D || | |||
| | |||
|- | |- | ||
| [[CECHMxx]] || 0x08 || [[VER-00x|VER-001]] || [[SW-301]]<br /> or<br />[[SW-302]] || 065D || | |||
| | |||
|- | |- | ||
| style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHNxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | |||
| | |||
|- | |- | ||
| style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHOxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | |||
| | |||
|- | |- | ||
| [[CECHPxx]] || 0x08 || [[VER-00x|VER-001]] || [[SW-301]]<br /> or<br />[[SW-302]] || 065D || | |||
| < | |||
|- | |- | ||
| [[CECHQxx]] || 0x08 || [[VER-00x|VER-001]] || [[SW-301]]<br /> or<br />[[SW-302]] || 065D || | |||
| | |||
|- | |- | ||
| [[CECH-20xx]] || 0x09 || [[DYN-00x|DYN-001]] || [[SW2-301]] || 0832 || | |||
|- | |- | ||
| | | [[CECH-21xx]] || 0x0A || [[SUR-00x|SUR-001]] || [[SW2-301]]<br /> or<br />[[SW2-302]] || 08C2 || | ||
|- | |- | ||
| | | [[CECH-25xx]] || 0x0B || [[JTP-00x|JTP-001]]<br /> or<br />[[JSD-00x|JSD-001]] || [[SW2-301]] or<br />[[SW2-302]] or<br />[[SW2-303]] || 08C2 || | ||
|- | |- | ||
| | | [[CECH-30xx]] || 0x0C || [[KTE-00x|KTE-001]] || [[SW2-301]] or<br />[[SW2-302]] or<br />[[SW2-303]] || 0918 || | ||
|- | |- | ||
| | | [[CECH-40xx]] || 0x0D || [[MSX-00x|MSX-001]]<br /> or<br />[[MPX-00x|MPX-001]] || [[SW3-302]] || 098F || | ||
|- | |- | ||
|} | |} | ||
=== | ==Prototypes== | ||
{| class="wikitable sortable" | |||
{| class="wikitable" | |||
|- | |- | ||
| | ! [[SKU Models|Model]] !! [[IDPS|Type]] !! [[Motherboard Revisions|Board]] !! [[Syscon Hardware|Syscon<br />part no.]] !! [[More System Information#First_section|Soft<br />Id.]] !! Active JTAG !! Notes | ||
|- | |- | ||
| | | [[DECR-1000|DECR1000(A/J)]] || 0x01 || [[TMU-520]] || [[CXR713F120A]] || 03FB || ? <!-- PS3NEWS says yes, but no proof --> || | ||
A | |||
< | |||
|- | |- | ||
| | | [[DEH-H1000A(S)(-E(S))]] || 0x01 || [[COK-001 (Prototype)]] || [[CXR713F120A]] || 0B67 || ? <!-- same SC, so yes --> || | ||
|- | |- | ||
| | | [[DEH-H1001-D]] || 0x01 || [[COOKIE-13]] || [[CXR713F120A]] || ?0B67? || ? <!-- PS3NEWS says yes, but no proof --> || | ||
|- | |- | ||
<!-- Not Prototype debug units - see retail --> | |||
|} | |} | ||
<br/> | |||
---- | |||
< | Not mentioned:<pre>08A0 - ?CBEH-H2001(B)? | ||
0F29 - ? | |||
0F38 - ?</pre> | |||
</ | |||
You can attach a 3.3v TTL cable (LV-TTL) to the UART on syscon | = Syscon UART = | ||
You can attach a 3.3v TTL cable (LV-TTL) to the UART on syscon. There is a simple plaintext protocol involved. This varies on different syscon models. Example: | |||
'''<command>:<hash>''' | '''<command>:<hash>''' | ||
Where the hash is the sum of command bytes & 0xFF | Where the hash is the sum of command bytes & 0xFF | ||
you should terminate commands with \r\n, the syscon messages are only terminated with \n | |||
Here are some of the commands/messages encountered: | Here are some of the commands/messages encountered: | ||
<pre> | |||
Messages: | Messages: | ||
Power applied (standby mode) | |||
OK 00000000:3A | OK 00000000:3A | ||
Line 461: | Line 101: | ||
No text, invalid hash: | No text, invalid hash: | ||
NG F0000002:4D | NG F0000002:4D | ||
Commands: | Commands: | ||
VER:ED | VER:ED | ||
OK 00000000 S1E 00 00 065D:A4 | OK 00000000 S1E 00 00 065D:A4 | ||
ERRLOG:CB | ERRLOG:CB | ||
Line 475: | Line 112: | ||
DATE:1E | DATE:1E | ||
NG F0000003:4E | NG F0000003:4E | ||
</pre> | </pre> | ||
{ | {{Models}} | ||
[[Category:System Controller]] |