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<div style="float:right">[[File:Syscon CXR713120-203GB DIE (detail).jpg|300px|thumb| Syscon CX'''R7131'''20-203GB DIE (detail)]]<br />[[File:Pyramid Syscon live probing.jpg|300px|thumb|Pyramid Syscon live probing]]</div>
== General Information ==


= Description =
Syscon is the main power controller chip. It is responsible for powering up the various power systems and for configuring and initialising the CELL, RSX and southbridge. It communicates with these devices via seperate SPI busses. There is external access by JTAG (Which appears to have been disabled after factory programming) and Serial.
The PS3 syscon is the main power controller chip of the PS3. It is responsible for powering up the main 12v rail of the [[Power Supply]] and various power systems by switching different [[Talk:Regulators|voltage regulators]] in the motherboard, and for configuring and initialising the [[CELL BE|BE]], [[RSX]] and [[South Bridge|SB]] via dedicated SPI buses.


The LEDs and buttons of the [[Switch boards|Switch board]] are connected to syscon, as well as the [[Cooling|fan/s]], buzzer, etc.
== Generation 1 ==
[[File:SYSCON_GEN1.JPG|thumb|Syscon 1st Generation (BGA Packaging)]]


The Syscon is a SoC and based on a ARM7TDMI-S (in the [[Mullion]] syscons) or a NEC 78K0R (in the [[Sherwood]] syscons) design. There is external access by "JTAG" (disabled from factory on retail models), an EEPROM programming interface (only on Mullion) and Serial (UART).
=== Packaging ===


<!--// Remote Power ON/OFF (from network, HDMI CEC commands, etc...) is managed by devices connected to the southbridge (ethernet/wifi/BT, HDMI controller, etc...) //-->
The first generation of the chip comes in a 200 pin BGA package as per below:


== PlayStation system controllers ==
<pre>
  T R P N M L K J H G F E D C B A
1 . . . . . . . . . . . . . . . .  1
2 . . . . . . . . . . . . . . . .  2
3 . .                        . .  3
4 . .  . . . . . . . . . .  . .  4
5 . .  . . . . . . . . . .  . .  5
6 . .  . . . . . . . . . .  . .  6
7 . .  . . . . . . . . . .  . .  7
8 . .  . . . .    . . . .  . .  8
9 . .  . . . .    . . . .  . .  9
10 . .  . . . . . . . . . .  . . 10
11 . .  . . . . . . . . . .  . . 11
12 . .  . . . . . . . . . .  . . 12
13 . .  . . . . . . . . . .  . . 13
14 . .                        . . 14
15 . . . . . . . . . . . . . . . . 15
16 . . . . . . . . . . . . . . . . 16
  T R P N M L K J H G F E D C B A
</pre>


{| class="wikitable" style="font-size:small; line-height:105%"
=== Pinout ===
! Production Start Date (<=) || PS2 Mechacon !! PSP Syscon !! PS3 Syscon !! PSVita Syscon !! PS4 Syscon !! Used IC/CPU Core
Work in progress
{|class="wikitable"
! Pin # !! Name !! Port !! Description
|-
| T2 || /BE_INT || rowspan="9" | Port M <br />Cell Control Line ||
|-
| R1 || PM7 ||
|-
| R2 || PM6 ||
|-
| P1 || BE_POWGOOD ||
|-
| P2 || /BE_RESET ||
|-
| N1 || BE_SPI_CLK || rowspan="4" | Cell SPI Bus
|-
| N2 || BE_SPI_DO
|-
| M1 || BE_SPI_DI
|-
| M2 || /BE_SPI_CS
|-
| L4 || PL8 || rowspan="9" | Port N || rowspan="9" | unused
|-
| L5 || PL7
|-
| K4 || PL6
|-
| K5 || PL5
|-
| J4 || PL4
|-
| J5 || PL3
|-
| H4 || PL2
|-
| H5 || PL1
|-
| H6 || PL0
|-
| A8 || SB_SPI_CLK || rowspan="8" | Port K || rowspan="4" | Southbridge SPI Bus
|-
| B8 || SB_SPI_DO
|-
| A9 || SB_SPI_DI
|-
| B9 || /SB_SPI_CS
|-
| A10 || SEL2_I2C_SCL ||
|-
| B10 || SEL2_I2C_SDA ||
|-
| A11 || ACDC_STBY ||
|-
| B11 || PK0 ||
|-
| B5 || PJ7 || rowspan="8" | Port J ||
|-
|-
| <abbr title="GH-001+">10/1999</abbr> || CXP101064 || - || - || - || - || rowspan="2" | Sony SPC970 (100 pin)
| A5 || DISC_OUT12_SW ||
|-
|-
| <abbr title="GH-003+">01/2000</abbr> || CXP102064 || - || - || - || -
| B2 || DISC_OUT8_SW ||
|-
|-
| <abbr title="GH-015+">09/2000</abbr> || CXP103049 || - || - || - || - || Sony SPC??? (136 pin)
| A2 || DISC_IN ||
|-
|-
| style="padding:0px" colspan="7" |
| B3 || SW_10 ||
|-
|-
| <abbr title="TMU-001, TMU-002, TA-079, TA-081">08/2004</abbr> || - || BAR''xx'' || - || - || - || NEC <abbr title="D790019">D780032AY</abbr> (78K0/78003xA, 64 pin)
| A3 || SW_0 ||
|-
|-
| <abbr title="TA-082, TA-086">07/2005</abbr> || - || B30''x'' || - || - || - || NEC <abbr title="D79F0036">D78F0531</abbr> (78K0/KE2 V2.00, 64 pin)
| B4 || SW_8_B ||
|-
|-
| <abbr title="TA-085, TA-088, TA-091, TA-094">07/2007</abbr> || - || B40''x'' / 40''xx'' || - || - || - || NEC <abbr title="D79F????">D78F0544</abbr> (78K0/KF2 V2.00, 84 pin)
| A4 || SW_8_C ||
|-
|-
| <abbr title="TA-090, TA-092, TA-093, TA-095, TA-096, TA-097">07/2008</abbr> || - || 3''xxx'' || - || - || - || NEC <abbr title="D79F????">D78F0534</abbr> (78K0/KE2 V2.00, 64 pin)
| L16 || SW_PCI || rowspan="6" | Port I ||
|-
|-
| style="padding:0px" colspan="7" |
| L15 || DISC_CHUCK ||
|-
|-
| <abbr title="GH-023+, XPD-001, XPD-005">03/2003</abbr> || CXR706080 || - || - || - || - || rowspan="3" | Sony SR11 (ARM7TDMI)<br>PS2 (''Dragon''): 164 pin<br>PS3 (''Donkey''): 200 pin
| M16 || DISC_PHOT_LED ||
|-
|-
| <abbr title="GH-032+">09/2004</abbr> || CXR716080 || - || CXR713120 || - || -
| M15 || SW_2 ||
|-
|-
| <abbr title="GH-061+">07/2007</abbr> || CXR726080 || - || CXR714120 || - || -
| N16 || DIAG_MODE ||
|-
|-
| style="padding:0px" colspan="7" |
| N15 || BACKUP_MODE ||
|-
|-
| 03/2008 || - || - || SW || - || - || NEC <abbr title="D79F0073">D78F11AA</abbr> (78K0R/KH3 V3.40, 128 pin)
| E6 || /HDMI_INT || rowspan="8" | Port H ||
|-
|-
| 05/2009 || - || - || SW2 || - || - || NEC <abbr title="D79F0086">D78F11BB</abbr> (78K0R/KH3 V1.00, 128 pin)
| D6 || VD_CECI0 ||
|-
|-
| <abbr title="IRT-001, IRT-002, IRS-002, IRS-1001, DOL-1001, DOL-1002">07/2010</abbr> || - || - || - || <abbr title="No official name">"SC"</abbr> || - || NEC <abbr title="No/Matching internal name">D79F0109</abbr> (<abbr title="Mix between 78K0R/KH3 and 78K0R/Kx3-L">78K0R/KH3-L</abbr> V1.00, 121 pin)
| E7 || PH5 ||
|-
|-
| 06/2011 || - || - || SW3 || - || - || NEC <abbr title="D79F0123">D78F11CC</abbr> (78K0R/KG3 V1.00, 100 pin)
| D7 || /RS_POW_FAIL ||
|-
|-
| style="padding:0px" colspan="7" |
| E8 || /MUL_CHKSTP_IN ||
|-
|-
| <abbr title="CVN-001, SAA-001, SAB-001">07/2013</abbr> || - || - ||- || - || C0L || Renesas R5F100PL (RL78/G13 V3.03, 100 pin)
| D8 || /MUL_TRG_IN ||
|-
|-
| <abbr title="USS-1001, USS-1002">08/2013</abbr> || - || - ||- || A0''xxx'' || - || Renesas R5F1ZCRK (RL78/G13 V3.03, 121 pin)
| E9 || /SYS_THR_ALRT ||
|-
|-
| <abbr title="SAC-001, SAD-001, SAD-002, SAD-003, SAE-001, SAE-002, SAE-003, SAE-004, SAF-004, SAF-006, HAC-001, NVA-001, NVB-003, NVB-004, NVG-001, NVG-002">04/2015</abbr> || - || - ||- || - || C0L2 || Renesas R5F101LL (RL78/G13 V3.03, 64 pin)
| D9 || /SB_INT ||
|-
|-
|}
| M11 || SW_ATA || rowspan="8" | Port G ||
 
|-
* The SPC900 core was designed by Texas Instruments ([https://www.linkedin.com/in/hirakawa-katsunobu-55b09b2])
| N11 || SW_4_A ||
* ''CXP101064'', ''CXP102064'' are similar to CXP97 (''CXP971000'', ''CXP972032'', '''CXP973064''', ''CXP973F064''), the ''CXP103049'' matches no COTS because of its OCD support
** In-Circuit-Emulator: Mitek NICE-SPC970 ([http://www.hitechfacility.co.jp/details.php?id=E0001913]); Debug software: SVD970; Flash programmer: SFP-2
* A ''F'' inside the model name specifies that the IC contains flash memory.
** Mass-produced CXR/SW units don't have/use program flash memory for updates, instead an encrypted firmware patch is stored on the data-"EEPROM"
* CXR7 series uses Sony SR11 CPU (ARM7TDMI)
** Models with public datasheet: ''CXR702080'', ''CXR702F080'', ''CXR704060'' (datasheet: [http://www.alldatasheet.com/datasheet-pdf/pdf/294279/SONY/CXR704060.html 1])
* Prototype PS3 Syscon's:
** [[CXR713F120A]] Syscon used on (early) pre-release prototypes, e.g. [[CEB-2030]], [[DECR-1000]], [[DEH-H1001-D]], [[DEH-H1000A-E]]
** [[DEH-FH1500J-A]] with [[VERTIGO-02]] board and SW series prototype ''[[Media:DEH-FH1500J-A_-_VERTIGO-02_-_Syscon_Hardware.jpg|D79F0073]]''
** [[CBEH-H2001]] with [[SUR-00x#SURTEES-03|SURTEES-03]] board and SW2 series prototype ''D79F0086''
** [[DEH-ML00AK-G]] with MPX-001 (Prototype) board and SW3 series prototype ''[[Media:DEH-ML00AK-G_Board_4.jpg|D79F0123]]''
 
= PS3 Syscon models =
{| class="wikitable" style="font-size:small; line-height:105%"
|-
|-
! colspan="10" | [[Mullion]] [[Syscon Hardware|Syscons]] !! rowspan="13" style="padding:1px" | !! colspan="8" | [[SKU Models|PS3 model]] & [[Motherboard Revisions|Motherboard]] compatibility by [[Platform ID]]
| M10 || /XDR_FET_VREF ||
|-
|-
! Model !! [[Syscon Firmware|Rev.]] !! [[Syscon Firmware|Ver.]] !! <abbr title="Syscon Firmware build date">Year</abbr> !! Package !! ROM !! FLASH !! colspan="2" | [[SC_EEPROM|EEPROM]] !! RAM
| N10 || /XDR_FET_SCK ||
! DEH-R10xx<br>[[DECR-1000]] !! [[SKU Models Nonretail|Prototypes]] !! [[CECHAxx]]<br>[[CECHBxx]] !! [[CECHCxx]]<br>[[CECHExx]] !! [[CECHGxx]] !! [[CECHHxx]] !! [[CECHJxx]]<br>[[CECHKxx]] !! [[DECR-1400]]
|-
|-
! style="width:115px; border-top:hidden" | !! style="width:35px; border-top:hidden" | !! style="width:55px; border-top:hidden" | !! style="width:30px; border-top:hidden" | !! style="width:60px; border-top:hidden" | !! style="width:40px; border-top:hidden" | !! style="width:40px; border-top:hidden" | !! style="width:35px" | Total !! style="width:35px" | Used !! style="width:35px; border-top:hidden" |
| M9 || BUZZER ||
! [[TMU-510]]<br>[[TMU-520]] !! <!--[[MPU-501]]<br>-->[[COOKIE-13]]<br>[[COK-001 (Prototype)|COK Proto]] !! [[COK-001]] !! [[COK-002]] !! [[SEM-001]] !! [[DIA-001]] !! [[DIA-002]] !! [[DEB-001]]
|-
|-
| colspan="18" style="padding:1px" |  
| N9 || SW_PWM ||
|-
|-
! [[CXR713F120A]]
| M8 || FANPWM1 ||
| colspan="3" style="text-align:center; background:#999; color:#fff" | <abbr title="Depends of the syscon firmware version installed in it">ANY</abbr> || rowspan="8" | [[Template:Syscon pinout BGA 200 pads|BGA 200]] || <abbr title="0x20000>128KB</abbr> || <abbr title="0x60000>384KB</abbr> || rowspan="4" | <abbr title="0x8000>32KB</abbr> || rowspan="3" | <abbr title="0x8000>32KB</abbr> || rowspan="8" | <abbr title="0x10000>64KB</abbr> || {{yes}}, factory || {{yes}}, factory || {{YES}} || {{YES}} || {{YES}} || {{YES}} || {{YES}} || {{YES}}
|-
|-
! [[CXR713120-201GB]]
| N8 || FANPWM0 ||
| 0B8E || v1.0.0_k1 || 2006 || rowspan="7" | <abbr title="0x60000>384KB</abbr> || rowspan="7" style="text-align:center; background:lightgrey;" | N/A || {{YES}} ? || {{YES}} ? || {{yes}}, factory || {{no}} || {{no}} || {{no}} || {{no}} || {{no}}
|-
|-
! [[CXR713120-202GB]]
| E10 || /MUL_CHKSTP_OUT || rowspan="8" | Port F ||
| 0C16 || v1.1.3_k1 || 2006 || {{YES}} ? || {{YES}} ? || {{YES}} || {{yes}}, factory || {{no}} || {{no}} || {{no}} || {{no}}
|-
|-
! [[CXR713120-203GB]]
| D10 || /MUL_TAG_OUT ||
| 0D52 || v1.2.3_k1 || 2007 || rowspan="5" | <abbr title="0x5000>20KB</abbr> || {{YES}} ? || {{YES}} ? || {{YES}} || {{YES}} || {{yes}}, factory || {{no}} || {{no}} || {{no}}
|-
|-
! [[CXR714120-301GB]]
| E11 || /SB_CGRESET ||
| 0DBF || v1.3.3_k1 || 2007 || rowspan="4" | <abbr title="0x5000>20KB</abbr> || {{YES}} ? || {{YES}} ? || {{YES}} || {{yes}}, <abbr title="Found in a CECHE01 MG (Metal Gear Solid 4 edition)">rare</abbr> || {{yes}}, factory || {{yes}}, factory || {{no}} || {{no}}
|-
|-
! [[CXR714120-302GB]]
| D11 || /SB_RESET ||
| 0E69 || v1.4.4_k2 || 2007 || {{YES}} ? || {{YES}} ? || {{YES}} || {{YES}} || {{YES}} || {{YES}} || {{yes}}, factory || {{yes}}, factory
|-
|-
! [[CXR714120-303GB]]
| E12 || BT_WAKEON ||
| 0F29 || v1.5.0_k2 || 2009 || {{YES}} ? || {{YES}} ? || {{YES}} || {{yes}}, <abbr title="Found in a refurbished CECHCxx/COK-002 with a 65nm RSX">refurb</abbr> || {{YES}} || {{YES}} || {{YES}} || {{YES}}
|-
|-
! [[CXR714120-304GB]]
| D12 || BE_VCS_1.25_ON ||
| 0F38 || v1.5.1_k2 || 2010 || {{YES}} ? || {{YES}} ? || {{yes}}, <abbr title="Found in a refurbished CECHAxx/COK-001 with a 40nm RSX">refurb</abbr> || {{YES}} || {{YES}} || {{yes}}, <abbr title="Found in a refurbished CECHHxx/DIA-001 with a 40nm RSX">refurb</abbr> || {{YES}} || {{YES}}
|}
 
{| class="wikitable" style="font-size:small; line-height:105%"
|-
|-
! colspan="10" | [[Sherwood]] [[Syscon Hardware|Syscons]] !! rowspan="17" style="padding:1px" | !! colspan="10" | [[SKU Models|PS3 model]] & [[Motherboard Revisions|Motherboard]] compatibility by [[Platform ID]]
| E13 || BE_VCS_1.30_ON ||
|-
|-
! Model !! [[Syscon Firmware|Rev.]] !! [[Syscon Firmware|Ver.]] !! <abbr title="Syscon Firmware build date">Year</abbr> !! Package !! ROM !! FLASH !! colspan="2" | [[SC_EEPROM|EEPROM]] !! RAM
| D13 || SW_1A ||
! [[SKU Models Nonretail|Prototypes]] !! [[CECHLxx]]<br>[[CECHMxx]]<br>[[CECHPxx]]<br>[[CECHQxx]] || [[SKU Models Nonretail|Prototypes]] || [[CECH-20xx]] !! [[CECH-21xx]] !! [[CECH-25xx]] !! [[SKU Models Nonretail|Prototypes]] || [[CECH-30xx]] !! [[CECH-40xx]] !! [[CECH-42xx]]<br>[[CECH-43xx]]
|-
|-
! style="width:115px; border-top:hidden" | !! style="width:35px; border-top:hidden" | !! style="width:55px; border-top:hidden" | !! style="width:30px; border-top:hidden" | !! style="width:60px; border-top:hidden" | !! style="width:40px; border-top:hidden" | !! style="width:40px; border-top:hidden" | !! style="width:35px" | Total !! style="width:35px" | Used !! style="width:35px; border-top:hidden" |
| A12 || /EJECT_SW || rowspan="8" | Port E ||
! [[VERTIGO-02|VERTIGO]]<br><small>prototype</small> !! [[VER-001]] !! [[SUR-00x#SURTEES-03|SURTEES]]<br><small>prototype</small> !! [[DYN-001]] !! [[SUR-001]] !! [[JTP-001]]<br>[[JSD-001]] !! [[MPX-001]]<br><small>prototype</small> !! [[KTE-001]] !! [[MSX-001]]<br>[[MPX-001]]<br>[[NPX-001]] !! [[PPX-001]]<br>[[PQX-001]]<br>[[RTX-001]]<br>[[REX-001]]
|-
|-
| colspan="18" style="padding:1px" |  
| B12 || /POW_SW ||
|-
|-
! [[Media:DEH-FH1500J-A_-_VERTIGO-02_-_Syscon_Hardware.jpg|D79F0073]]
| A13 || /SB_EBUS_RESET ||
| colspan="3" style="text-align:center; background:#999; color:#fff" | <abbr title="Depends of the syscon firmware version installed in it">ANY</abbr> || rowspan="7" | [[Template:Syscon pinout LQFP 128 pins|LQFP 128]] || rowspan="12" style="text-align:center; background:lightgrey;" | N/A || rowspan="3" | <abbr title="0x80000>512KB</abbr> || rowspan="12" style="text-align:center; background:lightgrey;" | N/A || rowspan="12" style="text-align:center; background:lightgrey;" | <abbr title="0x8000 Emulated inside FLASH">32KB</abbr> || rowspan="12" | <abbr title="0xC800>50KB</abbr> || {{yes}}, factory || {{YES}} || colspan="4" rowspan="3" style="text-align:center; background:#CC5555; color:#FFFFFF;" | No (<abbr title="Different HDMI/CEC handling">HDMI Incompatible</abbr>) || colspan="4" rowspan="7" style="text-align:center; background:#CC5555; color:#FFFFFF;" | No (different package)
|-
|-
! [[SW-301]]
| B13 || SB_EBUS_BRDY ||
| 065D || 0.17.0 || 2008 || {{YES}} ? || {{yes}}, factory
|-
|-
! [[SW-302]]
| A14 || PE3 ||
| <abbr title="Please help wiki by reporting this ID"><span style="background:#ff4444; color:#ffff00;">'''????'''</span></abbr> || <abbr title="Please help wiki by reporting this ID"><span style="background:#ff4444; color:#ffff00;">'''?.??.?'''</span></abbr> || 2008 || {{YES}} ? || {{yes}}, factory
|-
|-
! D79F0086
| B14 || VD_CECI1 ||
| colspan="3" style="text-align:center; background:#999; color:#fff" | <abbr title="Depends of the syscon firmware version installed in it">ANY</abbr> || rowspan="9" | <abbr title="0xC0000>768KB</abbr> || colspan="2" rowspan="4" style="text-align:center; background:#CC5555; color:#FFFFFF;" | No (<abbr title="Different HDMI/CEC handling">HDMI Incompatible</abbr>) || {{yes}}, factory || {{YES}} || {{YES}} || {{YES}}
|-
|-
! [[SW2-301]]
| A15 || /BE_POW_FAIL ||
| 0832 || 1.11.0 || 2009 || {{YES}} ? || {{yes}}, factory || {{no}} || {{no}}
|-
|-
! [[SW2-302]]
| B15 || /POW_FAIL ||
| 08A0 || 1.16.0 || 2009 || {{YES}} ? || {{YES}} || {{yes}}, factory || {{no}}
|-
|-
! [[SW2-303]]
| F13 || SW_5_B || rowspan="8" | Port D ||
| 08C2 || 1.21.0 || 2010 || {{YES}} ? || {{YES}} || {{YES}} || {{yes}}, factory
|-
|-
! [[Media:DEH-ML00AK-G_Board_4.jpg|D79F0123]]
| F12 || MK_EN ||
| colspan="3" style="text-align:center; background:#999; color:#fff" | <abbr title="Depends of the syscon firmware version installed in it">ANY</abbr> || rowspan="5" | [[Template:Syscon pinout LQFP 100 pins|LQFP 100]] || colspan="6" rowspan="5" style="text-align:center; background:#CC5555; color:#FFFFFF;" | No (different package) || {{yes}}, factory || {{YES}} || {{YES}} || {{YES}}
|-
|-
! [[SW3-301]]
| G13 || BEVRM_VID5 ||
| 0918 || 2.3.0 || 2011 || {{YES}} ? || {{yes}}, factory || {{no}} || {{no}}
|-
|-
! [[SW3-302]]
| G12 || BEVRM_VID4 ||
| 098F || 2.12.0 || 2012 || {{YES}} ? || {{YES}} || {{yes}}, factory || {{no}}
|-
|-
! [[SW3-303]]
| H13 || BEVRM_VID3 ||
| <abbr title="Please help wiki by reporting this ID"><span style="background:#ff4444; color:#ffff00;">'''????'''</span></abbr> || <abbr title="Please help wiki by reporting this ID"><span style="background:#ff4444; color:#ffff00;">'''?.??.?'''</span></abbr> || 2013 || {{YES}} ? || {{YES}} || ? || ?
|-
|-
! [[SW3-304]]
| H12 || BEVRM_VID2 ||
| 09A4 || 2.21.0 || 2013 || {{YES}} ? || {{YES}} || {{YES}} || {{yes}}, factory
|}
 
= Syscon Externalised Ports =
 
'''Note:''' for more specific information per model, see the links to each subpage in the Serialnumbers per SKU table.
 
== Syscon UART packets ==
 
=== SCUART daemon (SCUARTD) packet structure ===
 
SCUARTD packets includes header of 0x3 bytes and optional payload (depending on the command).
 
Packet IDs are not important, they are used only by clients and processed by SCUART daemon. SCUART daemon opens terminal file /dev/ttyS0 and use it to send commands and receive responses.
 
{| class="wikitable"
|-
|-
! Offset !! Size !! Description
| J13 || BEVRM_VID1 ||
|-
|-
| 0x00 || 0x01 || Magic?
| J12 || BEVRM_VID0 ||
|-
|-
| 0x01 || 0x01 || Payload size
| K13 || SW_HDD || rowspan="8" | Port C ||
|-
|-
| 0x02 || 0x01 || Command
| K12 || I2CBUS_EN ||
|-
|-
| 0x03 || Payload size || Payload data
| L13 || RSXVRM_VID5 ||
|-
|-
|}
| L12 || RSXVRM_VID4 ||
 
=== Packets ===
 
{| class="wikitable"
! Packet ID !! Command/Action !! Description !! Notes
|-
|-
| 0x00 || '''version''' || Firmware version || Gets installed syscon's firmware version (Note: backup bank contains version 0.4.5_b4 !! On CEB-2030 it is 0.3.0 )
| M13 || RSXVRM_VID3 ||
|-
|-
| 0x01 || '''bringup''' || Bring up || <!--// Standby->ON (Remote Power ON using an UART package, from [[Communication Processor]] ?) //-->
| M12 || RSXVRM_VID2 ||
|-
|-
| 0x02 || '''shutdown''' || Shutdown || <!--// ON->Standby (Remote Power OFF using an UART package, from [[Communication Processor]] ?) //-->
| N13 || RSXVRM_VID1 ||
|-
|-
| 0x03 || '''firmud''' || Firmware update || Notifies about firmware update operation
| N12 || RSXVRM_VID0 ||
|-
|-
| 0x04 || '''bsn''' || Board Serial Number || Retrieves syscon's Board Serial Number
| T15 || SW_8_A || rowspan="8" | Port B ||
|-
|-
| 0x05 || '''halt''' || Halt || Used at start of firmware update operation
| R14 || SW_7_A ||  
|-
|-
| 0x06 || '''cp ready''' || Communication Processor Ready || <!--// [[Communication Processor]] related, for [[SKU_Models_Nonretail#Reference_Tool_.28Tool.2FDECR.29 | Tool/DECR models]]  //-->
| T14 || SW_6 ||
|-
|-
| 0x07 || '''cp busy''' || Communication Processor Busy || <!--// [[Communication Processor]] related, for [[SKU_Models_Nonretail#Reference_Tool_.28Tool.2FDECR.29 | Tool/DECR models]] //-->
| R13 || SW_1_B ||
|-
|-
| 0x08 || '''cp reset''' || Communication Processor Reset || <!--// [[Communication Processor]] related, for [[SKU_Models_Nonretail#Reference_Tool_.28Tool.2FDECR.29 | Tool/DECR models]] //-->
| T13 || SW_4_B ||
|-
|-
| 0x09 || '''bestat''' || Cell B.E. status || Retrieves Cell B.E. status
| R12 || SW_3 ||
|-
|-
| 0x0A || '''powersw''' || Power switch || toggles power switch button short pressing
| T12 || VD_CECO1 ||
|-
|-
| 0x0B || '''resetsw''' || Reset switch || toggles reset switch button holding
| R11 || VD_CECO0 ||
|-
|-
| 0x0C || '''bootbeep stat''' || Boot Beep Status ||
| N7 || STBY_LED || rowspan="8" | Port A ||
|-
|-
| 0x0D || '''bootbeep on''' || Boot Beep On ||
| M7 || POW_LED ||
|-
|-
| 0x0E || '''bootbeep off''' || Boot Beep Off ||
| N6 || /AUDIO_MUTE ||
|-
|-
| 0x0F || ''Reset syscon'' || Reset Syscon || Resets syscon
| M6 || SW_7_B ||
|-
|-
| 0x10 || '''xdrdiag info''' || XDR diagnostics Information ||
| N5 || /BT_RESET ||
|-
|-
| 0x11 || '''xdrdiag start''' || XDR diagnostics Start || Starts XDR diagnostics
| M5 || /GBE_RESET ||
|-
|-
| 0x12 || '''xdrdiag result''' || XDR diagnostics Result || Gets a result of XDR diagnostics
| N4 || SW_5_A ||
|-
|-
| 0x13 || '''xiodiag''' || XIO diagnostics || Starts XIO diagnostics and gets a result of it
| M4 || SW_9 ||
|-
|-
| 0x14 || '''fandiag''' || Fan diagnostics || Retrieves RPMs of fans
| U16 || RBB || rowspan="12" | EEPROM Interface ||
|-
|-
| 0x15 || '''errlog''' || Error log || Retrieves a list of codes (with timestamps) of latest errors
| K16 || PI7 ||
|-
|-
| 0x16 || ''Read line'' || Read Line ||
| U15 || WCB ||
|-
|-
| 0x17 || '''tmpforcp <zone ID>''' || Reference Tool's temperature For Communication Processor || Gets the temperature of reference tool
| K15 || PI6 ||
|-
|-
| 0x18 || rowspan="8" colspan="3" style="background:lightgrey; color:#ff0000; text-align: center;" | Invalid CMDs
| E16 || SKB ||
|-
|-
| 0x19
| E15 || PP3 ||
|-
|-
| 0x1A
| G16 || DI ||
|-
|-
| 0x1B
| G15 || PP2 ||
|-
|-
| 0x1C
| H16 || DO ||
|-
|-
| 0x1D
| H15 || PP1 ||
|-
|-
| 0x1E
| F16 || CSB ||
|-
|-
| 0x1F
| F15 || PP0 ||
|-
|-
| 0x20 || '''cp beepremote''' || Communication Processor Beep Remote ||
| H11 || TESTMODE || rowspan="9" | Reset & Clock ||
|-
|-
| 0x21 || '''cp beep2kn1n3''' || ||
| B16 || OSCOUT ||
|-
|-
| 0x22 || '''cp beep2kn2n3''' || ||
| C16 || OSCIN ||
|-
|-
| ?? || '''csum''' || Checksum || Calculates the Checksum of something (No packet ID listing on scuartd)
| D16 || 32KOUT ||
|-
|-
| ?? || '''osbo''' || ?Operating System Boot? || No idea what this does, but returns <pre>done</pre> when it's sent <!--Operative System Boot Order ?... something related with gameOS/otherOS boot flag ? -->
| D15 || 32KIN ||
|-
|-
| ?? || '''scopen''' || Syscon Open || returns SC_READY or ERROR 1
| T5 || EXTAL ||
|-
|-
| ?? || '''scclose''' || Syscon Close || ???
| T4 || XTAL ||
|-
|-
| ?? || '''ejectsw''' || Eject Switch || toggles eject switch button pressing (3 beeps)
| T7 || XXTALO ||
|-
|-
|}
| J11 || /RST ||
 
=== Packets Logs ===
 
{| class="wikitable"
! Packet ID !! Command/Action !! Logs !! Notes
|-
|-
| 0x00 || '''version''' || version\nv1.0.4_c2\n  (END) ||
| R4 || AVSUO || rowspan="35" | Power Port || Ground
|-
|-
| 0x01 || '''bringup''' || (END) ||
| R5 || AVDUO || +3.3v
|-
|-
| 0x02 || '''shutdown''' || Do nothing. (PowerOff State)\n (END) || Returns (END) if the system is on
| G6 || AVSS || Ground
|-
|-
| 0x03 || '''firmud''' || Start...\nErase User Program Area\n  (END) || This will brick your SYSCON if you don't feed it any argument or feed to it the wrong argument!
| C2 || AVREF2 || Ground
|-
|-
| 0x04 || '''bsn''' || bsn\nNANNNNNNNNNA\n  (END) || N is digit and A is char (removed for privacy)
| B1 || AVREF1 || +3.3v
|-
|-
| 0x05 || '''halt''' || halt\n  (END) ||
| F7 || AVDD || +3.3v
|-
|-
| 0x06 || '''cp ready''' || cp ready\nCP READY: OK\n  (END) ||  
| K11 || VSSF || Ground
|-
|-
| 0x07 || '''cp busy''' || cp ready\nCP BUSY: OK\n  (END) || STATUS light blinks forever
| K6 || VSSF || Ground
|-
|-
| 0x08 || '''cp reset''' || No response || Should reset CP to factory settings
| L6 || VDDF || +3.3v
|-
|-
| 0x09 || '''bestat''' || (PowerOff State)\n (END) ||
| G7 || rowspan="8" | VSS || rowspan="8" | Ground
|-
|-
| 0x0A || '''powersw''' || (END) ||
| G8
|-
|-
| 0x0B || '''resetsw''' || (END) ||
| G10
|-
|-
| 0x0C || '''bootbeep stat''' || BOOT BEEP: ON\n  (END) || when it's off BOOT BEEP status changes to OFF
| T6
|-
|-
| 0x0D || '''bootbeep on''' || BOOT BEEP ON: DONE\n  (END) ||
| R6
|-
|-
| 0x0E || '''bootbeep off''' || BOOT BEEP OFF: DONE\n  (END) ||
| T3
|-
|-
| 0x0F || '''Reset syscon''' || ||
| L1
|-
|-
| 0x10 || '''xdrdiag info''' || 32\n  (END) ||
| E1
|-
|-
| 0x11 || '''xdrdiag start''' || DIAG START\n  (END) ||
| C15 || VSSep || Ground
|-
|-
| 0x12 || '''xdrdiag result''' || XDR OK\n  (END) || will return ERROR NOT STARTED if xdrdiag start wasn't run previously
| G11 || VDDep || +3.3v
|-
|-
| 0x13 || '''xiodiag''' || 0 903\n  (END) ||
| F11 || VDDbat || +battery
|-
|-
| 0x14 || '''fandiag''' || ERROR FAN ACTIVE\n  (END) ||
| H7 || rowspan="7" | DVDD || rowspan="7" | +1.8v
|-
|-
| 0x15 || '''errlog''' || ofst[ %d]:err_code:0x%08X, clock:0x%08X  YYYY/MM/DD HH:MM:SS || bunch of error logs. ends with (END) once they're over
| U10
|-
|-
| 0x16 || '''Read line''' || ||
| K10
|-
|-
| 0x17 || '''tmpforcp <zone ID>''' ||
| L10
|-
|-
| 0x20 || '''cp beepremote''' || (END) ||
| L11
|-
|-
| 0x21 || '''cp beep2kn1n3''' || (END) || sends a beep different than SYSCON beep :)
| R7
|-
|-
| 0x22 || '''cp beep2kn2n3''' || (END) || sends two beeps different than SYSCON beeps :)
| J7
|-
|-
| rowspan="8" | ?? || rowspan="8" | '''csum''' || Checksum: [027460C9] [68269779] [C19A855E]\n  (END) || displays 3 hexadecimal numbers inside rect parenthesis. the numbers are always the same, except when syscon version changes (v1.0.5_c1)
| F8 || rowspan="5" | VDD3 || rowspan="5" | +3.3v
|-
|-
| Checksum: [02746F91] [682F04DA] [27688CF5]\n  (END) || Another response (v1.0.4_c2)
| F10
|-
|-
| Checksum: [0274C877] [684DA659] [EA426BB1]\n  (END) || Another response (v1.0.4_c1)
| H10
|-
|-
| Checksum: [027B4064] [6B450C64] [4FBF6DA3]\n  (END) || Another response (v1.0.3_c1)
| J6
|-
|-
| Checksum: [027E1B71] [6CDA9F25] [E0C67065]\n  (END) || Another response (v1.0.1_c1)
| F6
|-
|-
| Checksum: [02812855] [6E83917C] [D40F70A5]\n  (END) || Another response (v0.9.14_c1)
| D2 || VDD2 || +1.5V_RSX_VDDIO
|-
|-
| Checksum: [02835059] [6FC5C632] [BB9BBEC3]\n  (END) || Another response (v0.9.9_c1)
| R3 || VDD1 || +1.2V_MC2_VDDIO
|-
|-
| Checksum: [026F7951] [66CB09FF] [4EA06B56]\n  (END) || Another response (v0.8.4_c8)
| L2 || VDD0 || +1.2V_MC2_VDDIO
|-
|-
| ?? || '''osbo''' || done\n  (END) ||
| A16 || rowspan="6" colspan="3"| NC
|-
|-
| ?? || '''scopen''' || SC_READY\nERROR 1\n\n*** Invalid Argument ***\n\n[mullion]$ ||
| T16
|-
|-
| ?? || '''scclose''' || \n\n\nSC_SUCCESS\n\n[mullion]$ ||
| T1
|-
|-
|}
| A1
 
=== Notes ===
 
* Some commands are unavailable on earlier firmwares, for example, tmpforcp is only supported on 1.3.3+.
* Some commands are divided into several strings, the first part (if exists) describes a command group, the second part describes the actual command and other parts describes command arguments.
* Real syscon commands have an ASCII form (a bold text in the 2nd column) instead of bytes above.
* Packet with ID *0x03* notifies syscon and calls SX program (based on ZMODEM protocol) to send firmware, syscon have custom or original implementation of RX program to receive firmware. An implementation of ZMODEM protocol used by Sony: http://oss.sony.net/Products/Linux/Others/Download/DECR-1000/mips_fp_le-lrzsz-0.12.20-devtool.1.src.rpm
 
A start of syscon's update procedure:
* A CP development tool includes several scripts which are participated in syscon update procedure. It starts after a CP update via ''update_syscon.pl'' perl script.
* This script checks the current syscon's firmware version. If it is in mask rom then it skips an update procedure, if not it checks major/minor/release parts of both versions and if a new version is applicable then it launches ''scfirmup'' utility and pass the firmware file path as an argument.
* ''scfirmup'' is a stupid tool which prepares a connection to SCUARTD and sends an update packet with a file path inside it. There is no need to comment it, here is reimplementation: http://pastie.org/private/6h8mfeoics4mdxear7ayg
 
A syscon's update operation in '''SCUARTD''' consists of following steps:
* 1. Check if ''SX'' program presents in ''/usr/bin/sx''. It should be a regular file.
* 2. Check if specified firmware file is a regular file.
* 3. Halt syscon by sending command '''halt'''  to UART, then wait some time until it prints ''HALT: OK''.
* 4. Reset syscon by sending byte ''0x30'' to GPIO register '''SC_PI0_DIPSW''', byte ''0x30'' to GPIO register '''SC_RSTX''', waiting 1 second and writing byte ''0x31'' to GPIO register '''SC_RSTX'''.
* 5. Get current syscon's firmwave version by sending command '''version''' to UART. After receiving it, look for a character after the first ''_'' (underscore) symbol from the left side of string and if it equals to the character ''b'', then proceed to the next step, otherwise go to the (8) step. (It is possible to patch this step to allow upgrading or downgrading at will)
* 6. Prepare syscon for an update by sending command '''firmud''' to UART, then fork the current process; the current process won't finish until a message ''Done'' from UART arrives (it is the end of update operation).
* 7. In the forked process start ''SX'' program and pass firmware file path to it. ''SX'' program reads firmware file and transfer each chunk of it to syscon.
* 8. After successful update operation reset syscon (a different way) by sending byte ''0x31'' to GPIO register '''SC_PI0_DIPSW''', byte ''0x30'' to GPIO register '''SC_RSTX''', waiting 1 second and writing byte ''0x31'' to GPIO register '''SC_RSTX'''.
 
Notes:
* It seems all scuartds checks firmware revision and probably syscon is updated only once (after factory).
* To be able to reflash it you need to patch ''SCUARTD'' or do a manual update without the use of ''SCUARTD''.
* You need to patch a single byte in ''SCUARTD'' to be able to flash any firmware (for example, to downgrade your syscon).
<syntaxhighlight lang="asm">
.text:00403A94: /* scuartd from CP 1.3.3 */
lb      $v1, 1($v0)
li      $v0, "b" /* 62 00 02 24 -> 63 00 02 24 */
bne    $v1, $v0, loc_4039F4
move    $a0, $zero
</syntaxhighlight>
 
* An actual firmware update process (without halting and resetting steps) takes about 1 minute.
* You cannot install a corrupted firmware with scfirmup unless you corrupt the header! It seems there is a hash of sorts (possibly of the plaintext) in the header preventing scfirmup from installing something corrupt
* Updating SYSCON requires the DECR to be in standby mode! You cannot update it while it is on.
* Corrupting the header and the body will make firmup install the SYSCON update anyways! be careful not to do it!
* Should you brick SYSCON, here's a patch to "unbrick" it, do not use it unless you brick it though!
<syntaxhighlight lang="asm">
.text:004038C0:
lw      $a0, 4($s4)
li      $a1, 0x400000
nop
addiu  $a1, (aHalt - 0x400000)  # "halt"
la      $t9, scuartd_send_sccmd
nop
jalr    $t9 ; scuartd_send_sccmd
nop
lw      $gp, 0x1E8+var_1D8($sp)
bnez    $v0, loc_4039B4 /* 33 00 40 14 -> 33 00 40 10 */
li      $a0, 1
</syntaxhighlight>
* You can use this bruteforcer to try your luck when finding new packets: https://hastebin.com/vomogesaru.cpp
 
== Syscon UART ==
{| class="wikitable"
! BGA !! Name !! Description
|-
|-
| P16 || UART0_TxD || Serial Transmit
| G9
|-
|-
| P15 || UART0_RxD || Serial Receive
| F9
|-
|-
|}
| L8 || JRTCK || rowspan="6" | JTAG Interface ||
 
<gallery>
File:COK-001 SC UART testpads.jpg|[[COK-001]] SC UART testpads
File:COK-002 SC UART testpads.jpg|[[COK-002]] SC UART testpads
File:SEM-001 SC UART testpads.jpg|[[SEM-001]] SC UART testpads
File:DIA-001 SC UART testpads.jpg|[[DIA-001]] SC UART testpads
File:DIA-002 SC UART testpads.jpg|[[DIA-002]] SC UART testpads
File:VER-001 SC UART testpads.jpg|[[VER-001]] SC UART testpads
File:DYN-001 SC UART testpads.jpg|[[DYN-001]] SC UART testpads
File:SUR-001 SC and SB UART testpads.jpg|[[SUR-001]] SC and SB UART testpads
File:JTP-001 SC and SB UART testpads.jpg|[[JTP-001]] SC and SB UART testpads
File:JSD-001 SC and SB UART testpads.jpg|[[JSD-001]] SC and SB UART testpads
File:KTE-001 SC and SB UART testpads.jpg|[[KTE-001]] SC and SB UART testpads
File:SW3 SC UART testpads.jpg|SW3 SC UART testpads
</gallery>
 
You can attach a 3.3v TTL cable (LV-TTL) to the UART on syscon (UART0_TxD, UART0_RxD). Baud rate is 57600. There is a simple plaintext protocol involved. This varies on different syscon models. Example:
 
'''<command>:<hash>'''
 
Where the hash is the sum of command bytes & 0xFF.
 
You should terminate commands with \r\n, the syscon messages are only terminated with \n.
 
=== Samples ===
 
Here are some of the commands/messages encountered:
 
Messages:
<pre>Power applied (standby mode)
OK 00000000:3A
 
Power on
# (PowerOn State):7F
 
Power off (Hard shutdown)
# (PowerOff State):DD
 
After Fan test:
# (PowerOff State) (Fatal):36
 
No text, invalid hash:
NG F0000002:4D</pre>
 
Commands:
<pre>
VER:ED
OK 00000000 S1E 00 00 065D:A4
OK 00000000 S1E 01 0B 00 0832:A3 (on DYN-001 board)
OK 00000000 S1E 02 03 00 0918:9A (on KTE-001 board)
 
ERRLOG:CB
OK 00000000:3A
 
DATE:1E
NG F0000003:4E
 
C:F1:BUZ
E:4F:NG F0000004
E:50:NG F0000005 (in DIAG mode)
 
C:D0:CID
E:50:NG F0000005
 
C:D0:CID GET
E:50:NG F0000005
 
C:DA:EEP
E:50:NG F0000005
 
C:DA:EEP GET
E:50:NG F0000005
 
C:E6:EEP SET
E:50:NG F0000005
 
C:D5:FAN
E:50:NG F0000005
 
C:83:FAN START
E:50:NG F0000005
 
C:3B:FAN STOP
E:50:NG F0000005
 
C:F4:KSV
E:50:NG F0000005
 
C:ED:REV
E:50:NG F0000005
 
C:F8:SPU
E:50:NG F0000005
 
C:FD:AUTH1
0000802000000000003000309C0EDB3F
E603EDB98A38DDC09400A2AB2DDE8CAB
0AECFE951FF7E2E8D8A7CF2202719F81
2F36DE83B424C27063C274CB0000E46B
<Important Note: 0x40 bytes>
                 
E:5D:NG E00000C0
 
C:34:BOOT
E:50:NG F0000005
</pre>
 
See also [[Talk:System_Controller_Firmware#Syscon_commands|Syscon commands]].
 
Bruteforcing commands:<!--// LOL //--> http://pastebin.com/CNei0xbC
 
VERY IMPORTANT:
* Max size of a command is 11 characters, 16 if you count with C:<hash>:
* Sending a command with 11 chars results in NO OUTPUT
* Sending a command with more than 11 chars results in NG F0000002
* Max size of a command on DECR is 135, 140 if you count with C:<hash>:
 
== Pinouts ==
See:
*https://www.psdevwiki.com/ps3/Template:Syscon_pinout_BGA_200_pads
*https://www.psdevwiki.com/ps3/Template:Syscon_pinout_LQFP_128_pins
*https://www.psdevwiki.com/ps3/Template:Syscon_pinout_LQFP_100_pins
 
{| class="wikitable" style="float:left; margin:5px;"
|+Syscon EEPROM (SPI)
! BGA !! Name !! Description
|-
|-
| F16 || CSB || Chip Select (needs to be low)
| K8 || JTCK ||
|-
|-
| H16 || DO || Serial Data Output
| K9 || JTDO ||
|-
|-
| G16 || DI || Serial Data Input
| L9 || JTMS ||
|-
|-
| E16 || SKB || Serial Data Clock
| K7 || JTDI ||
|-
|-
| J15 || WCB || Write Protect
| L7 || JNTAST ||
|-
|-
| J16 || RBB || Ready/Busy
| A6 || PR3 || rowspan="4" | Port R ||
|-
|-
| G11 || VDDep || + 3.3V
| B6 || MC_P_OFF_REQ ||
|-
|-
| C15 || VSSep || GND
| A7 || MC_ALIVE ||
|-
|-
|}
| B7 || MC_RESERVED1 ||
 
{| class="wikitable" style="float:left; margin:5px;"
|+Syscon BE SPI Bus
! BGA !! Name !! Description
|-
|-
| M2 || BE_SPI_CS || Chip Select
| R10 || RMC_IN || rowspan="7" | Port Q ||
|-
|-
| N2 || BE_SPI_DO || Serial Data Output
| T11 || PQ5 ||
|-
|-
| M1 || BE_SPI_DI || Serial Data Input
| T10 || PQ4 ||
|-
|-
| N1 || BE_SPI_CLK || Serial Data Clock
| T8 || SEL2_IEC_SCL ||
|-
|-
| colspan="3" {{cellcolors|lightblue}}
| T9 || SEL2_I2C_SDA ||
|-
|-
| P2 || BE_RESET || CellBE Reset
| R9 || PQ1 ||
|-
|-
| P1 || BE_POWGOOD  || CellBE PowerGood
| R8 || RSX_FBVDD_SEL ||
|-
|-
| T2 || BE_INT || CellBE Interrupt
| P16 || UART0_TxD || rowspan="4" | Port P || Serial Transmit
|-
|-
|}
| P15 || UART0_RxD || Serial Receive
 
{| class="wikitable" style="float:left; margin:5px;"
|+Syscon RSX SPI Bus
! BGA !! Name !! Description
|-
|-
| E2 || RSX_SPI_CS || Chip Select
| R16 || SEL1_I2C_SCL ||
|-
|-
| F2 || RSX_SPI_DO || Serial Data Output
| R15 || SEL1_I2C_SDA ||
|-
|-
| F1 || RSX_SPI_DI || Serial Data Input
| D1 || SEL0_I2C_SCL || rowspan="10" | Port O
|-
|-
| G1 || RSX_SPI_CLK || Serial Data Clock
| C1 || SEL0_I2C_SDA ||
|-
|-
| colspan="3" {{cellcolors|lightblue}}
| G4 || PO7 ||
|-
|-
| G2 || RSX_RESET || RSX Reset
| F4 || HDMI_RST0 ||
|-
|-
| J2 || RSX_INT || RSX Interrupt
| G5 || PO5 ||
|-
|-
|}
| F5 || DISC_IN_MECHA ||
 
{| class="wikitable" style="float:left; margin:5px;"
|+Syscon SB SPI Bus
! BGA !! Name !! Description
|-
|-
| B9 || SB_SPI_CS || Chip Select
| E4 || EJECT_MECHA ||
|-
|-
| B8 || SB_SPI_DO || Serial Data Output
| D4 || /XDR_FET_RST ||
|-
|-
| A9 || SB_SPI_DI || Serial Data Input
| E5 || /GX_VSRST ||
|-
|-
| A8 || SB_SPI_CLK || Serial Data Clock
| D5 || XCG_EN ||
|-
|-
| colspan="3" {{cellcolors|lightblue}}
| K2 || /VD_VINT1 || rowspan="11" | Port N ||
|-
|-
| D11 || SB_RESET || SB Reset
| K1 || /VD_VINT0 ||
|-
|-
| D9 || SB_INT || SB Interrupt
| J2 || /RSX_INT ||
|-
|-
|}
| J1 || RSX_FLDO ||
 
{| class="wikitable" style="float:left; margin:5px;"
|+Syscon JTAG (disabled in factory after production on retail models)
! BGA !! Name !! Description
|-
|-
| L8 || JRTCK || Return Test Clock
| H2 || PN6 ||
|-
|-
| K8 || JTCK || Test Clock
| H1 || PN5 ||
|-
|-
| K9 || JTDO || Test Data Out
| G2 || /RSX_RESET ||
|-
|-
| L9 || JTMS || Test Mode State / Test Mode Select
| G1 || RSX_SPI_CLK || rowspan="4" | RSX SPI Bus
|-
|-
| K7 || JTDI || Test Data In
| F2 || RSX_SPI_DO
|-
|-
| L7 || JNTRST || Test Reset
| F1 || RSX_SPI_DI
|-
|-
| E2 || /RSX_SPI_CS
|}
|}


= Testpads and alternative solder points =
*The identification of the syscon UART testpads can be made by grouping the motherboard models in a similar way we was doing with the [[Teensy%2B%2B_2.0#Schematics_by_motherboard_.28retail.29| layouts]] of the hardware flashers, there are 7 retail testpads layouts:
**Layout 1 = COK-001, COK-002 (fat, mullion, NAND)
**Layout 2 = SEM-001 (fat, mullion, NAND)
**Layout 3 = DIA-001, DIA-002 (fat, mullion, NOR)
**Layout 4 = VER-001 (fat, sherwood, NOR)
**Layout 5 = DYN-001 (slim, sherwood, NOR)
**Layout 6 = SUR-001, JTP-001, JSD-001, KTE-001 (slim, sherwood, NOR)
**Layout 7 = MSX-001, MPX-001, NPX-001, PPX-001, PQX-001, RTX-001, REX-001 (superslim, sherwood, NOR/eMMC)


== DIA-001 and DIA-002 ==
This points are availables to intercept signals by soldering wires, attaching probes, osciloscopes, etc... The photos are only orientatives to follow the traces, there's no need to remove the SYSCON to intercept this signals so can be done while its working


All this points has been hardware reverse engineered from a [[CECHHxx|CECHH02]]/[[DIA-00x#DIA-001|DIA-001]] motherboard
== Generation 2 ==
{{clear}}
[[File:SYSCON_GEN2.JPG|thumb|Syscon 2nd Generation (QFP Packaging)]]
 
QFP Package : 128 pins


Currently there is no known pin labelling for this generation
== CECHG02 Pinout ==
=== Topside Pinout ===
=== Topside Pinout ===
<div style="float:right">[[File:syscon_top.jpg|thumbnail|Syscon Top Pinouts<br />[[CECHHxx|CECHH02]]/[[DIA-00x#DIA-001|DIA-001]]]]</div>
[[File:syscon_top.jpg|thumbnail|Syscon Top Pinouts]]


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=== Bottomside Pinout ===
=== Bottomside Pinout ===
<div style="float:right">[[File:DIA-001 SysCon EPROM Interface.png|thumbnail|[[DIA-001]] [[CECHHxx]] [[SC EEPROM]] Interface]]<br />[[File:syscon_bottom.jpg|thumbnail|Syscon Bottom Pinouts<br />[[CECHHxx|CECHH02]]/[[DIA-00x#DIA-001|DIA-001]]]]<br />[[File:Syscon uart soldered on dia-002.jpg|thumbnail|Syscon UART soldered<br />[[CECHJxx]]/[[CECHKxx]] [[DIA-00x#DIA-002|DIA-002]]]]</div>
[[File:syscon_bottom.jpg|thumbnail|Syscon Bottom Pinouts]]


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{{Motherboard Components}}<noinclude>[[Category:Main]]</noinclude>
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