Editing Syscon Hardware
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== General Information == | |||
Syscon is the main power controller chip. It is responsible for powering up the various power systems and for configuring and initialising the CELL, RSX and southbridge. It communicates with these devices via seperate SPI busses. There is external access by JTAG (Which appears to have been disabled after factory programming) and Serial. | |||
== Generation 1 == | |||
[[File:SYSCON_GEN1.JPG|thumb|Syscon 1st Generation (BGA Packaging)]] | |||
=== Packaging === | |||
The first generation of the chip comes in a 200 pin BGA package as per below: | |||
<pre> | <pre> | ||
T R P N M L K J H G F E D C B A | |||
1 . . . . . . . . . . . . . . . . 1 | |||
2 . . . . . . . . . . . . . . . . 2 | |||
3 . . . . 3 | |||
4 . . . . . . . . . . . . . . 4 | |||
5 . . . . . . . . . . . . . . 5 | |||
6 . . . . . . . . . . . . . . 6 | |||
7 . . . . . . . . . . . . . . 7 | |||
8 . . . . . . . . . . . . 8 | |||
9 . . . . . . . . . . . . 9 | |||
10 . . . . . . . . . . . . . . 10 | |||
11 . . . . . . . . . . . . . . 11 | |||
12 . . . . . . . . . . . . . . 12 | |||
13 . . . . . . . . . . . . . . 13 | |||
14 . . . . 14 | |||
15 . . . . . . . . . . . . . . . . 15 | |||
16 . . . . . . . . . . . . . . . . 16 | |||
T R P N M L K J H G F E D C B A | |||
E | |||
C | |||
E | |||
C | |||
</pre> | </pre> | ||
=== Pinout === | |||
Work in progress | |||
{|class="wikitable" | |||
! Pin # !! Name !! Port !! Description | |||
== | |||
{| class="wikitable" | |||
! | |||
|- | |- | ||
| | | T2 || /BE_INT || rowspan="9" | Port M <br />Cell Control Line || | ||
|- | |- | ||
| | | R1 || PM7 || | ||
|- | |- | ||
| | | R2 || PM6 || | ||
|- | |- | ||
| | | P1 || BE_POWGOOD || | ||
|- | |- | ||
| | | P2 || /BE_RESET || | ||
|- | |- | ||
| | | N1 || BE_SPI_CLK || rowspan="4" | Cell SPI Bus | ||
|- | |- | ||
| | | N2 || BE_SPI_DO | ||
|- | |- | ||
| | | M1 || BE_SPI_DI | ||
|- | |- | ||
| | | M2 || /BE_SPI_CS | ||
| | |||
|- | |- | ||
| | | L4 || PL8 || rowspan="9" | Port N || rowspan="9" | unused | ||
|- | |- | ||
| | | L5 || PL7 | ||
|- | |- | ||
| | | K4 || PL6 | ||
|- | |- | ||
| | | K5 || PL5 | ||
|- | |- | ||
| | | J4 || PL4 | ||
|- | |- | ||
| | | J5 || PL3 | ||
|- | |- | ||
| | | H4 || PL2 | ||
|- | |- | ||
| | | H5 || PL1 | ||
|- | |- | ||
| | | H6 || PL0 | ||
| | |||
|- | |- | ||
| | | A8 || SB_SPI_CLK || rowspan="8" | Port K || rowspan="4" | Southbridge SPI Bus | ||
|- | |- | ||
| | | B8 || SB_SPI_DO | ||
|- | |- | ||
| | | A9 || SB_SPI_DI | ||
|- | |- | ||
| | | B9 || /SB_SPI_CS | ||
|- | |- | ||
| | | A10 || SEL2_I2C_SCL || | ||
|- | |- | ||
| | | B10 || SEL2_I2C_SDA || | ||
|- | |- | ||
| | | A11 || ACDC_STBY || | ||
|- | |- | ||
| B11 || PK0 || | |||
|} | |} | ||
= | == Generation 2 == | ||
[[File:SYSCON_GEN2.JPG|thumb|Syscon 2nd Generation (QFP Packaging)]] | |||
QFP Package : 128 pins | |||
Currently there is no known pin labelling for this generation | |||
== CECHG02 Pinout == | |||
=== Topside Pinout === | === Topside Pinout === | ||
[[File:syscon_top.jpg|thumbnail|Syscon Top Pinouts]] | |||
{|class="wikitable" | {|class="wikitable" | ||
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=== Bottomside Pinout === | === Bottomside Pinout === | ||
[[File:syscon_bottom.jpg|thumbnail|Syscon Bottom Pinouts]] | |||
{|class="wikitable" | {|class="wikitable" | ||
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|Unknown | |Unknown | ||
|} | |} | ||