Editing Syscon Hardware
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== General Information == | |||
Syscon is the main power controller chip. It is responsible for powering up the various power systems and for configuring and initialising the CELL, RSX and southbridge. It communicates with these devices via seperate SPI busses. There is external access by JTAG (Which appears to have been disabled after factory programming) and Serial. | |||
== Generation 1 == | |||
[[File:SYSCON_GEN1.JPG|thumb|Syscon 1st Generation (BGA Packaging)]] | |||
BGA Package : 200 Pins | |||
Pin's are labelled in the service manual for this generation | |||
== | == Generation 2 == | ||
[[File:SYSCON_GEN2.JPG|thumb|Syscon 2nd Generation (QFP Packaging)]] | |||
QFP Package : 128 pins | |||
Currently there is no known pin labelling for this generation | |||
== CECHG02 Pinout == | |||
=== Topside Pinout === | === Topside Pinout === | ||
[[File:syscon_top.jpg|thumbnail|Syscon Top Pinouts]] | |||
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=== Bottomside Pinout === | === Bottomside Pinout === | ||
[[File:syscon_bottom.jpg|thumbnail|Syscon Bottom Pinouts]] | |||
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|Unknown | |Unknown | ||
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