Editing Hardware flashing
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[[Category:Hardware]] | |||
[[File:PS3_Hardware.JPG | [[File:PS3_Hardware.JPG|thumb|Typical NOR flashing requires 16 Data wires, 23 Address wires and 3-4 control wires]] | ||
Both early launch consoles which feature [http://www.ps3devwiki.com/index.php?title=Flash_%28Hardware%29#NAND NAND flash] memory and later consoles which feature [http://www.ps3devwiki.com/index.php?title=Flash_%28Hardware%29#NOR NOR flash] memory are able to be flashed. Currently the preferred method of flashing the dual-NAND consoles is by using an infectus modchip or similar. | |||
Both early launch consoles which feature [ | |||
Marcan has made a NOR flasher / address sniffer for his PS3 slim by re-purposing a FPGA board made for Wii hacking. noralizer is a git repo that contains the HDL (verilog) and associated host computer tools for flashing/sniffing. There are ~50 signals to solder. Some PS3s contain two [http://www.ps3devwiki.com/index.php?title=Flash_%28Hardware%29#NAND NAND flashes] (block devices, that interleave their data unlike [http://www.ps3devwiki.com/index.php?title=Flash_%28Hardware%29#NOR NOR flash]). | |||
Marcan has made a | |||
Work is currently underway to brink a low cost AVR based NOR flasher that is capable of reading and writing on all consoles by defyboy. | |||
= NOR Interface Testpoints = | |||
Probably to aid in factory programming, Sony provides NOR testpoints on the bottomside of the motherboard. There are 16 data lines (Word access) and generally 23 Address lines. You will also need to control Chip Enable (#CE), Write Enable (#WE), Tristate (SB_DISABLE) and for some boards Write Protect (#WP) | Probably to aid in factory programming, Sony provides NOR testpoints on the bottomside of the motherboard. There are 16 data lines (Word access) and generally 23 Address lines. You will also need to control Chip Enable (#CE), Write Enable (#WE), Tristate (SB_DISABLE) and for some boards Write Protect (#WP) | ||
== Tristate == | |||
Tristate, or as it is referred to in the service manuals SB_DISABLE exists solely for the purpose of placing the [[South Bridge]] pins into high-impedance ( | Tristate, or as it is referred to in the service manuals SB_DISABLE exists solely for the purpose of placing the [[South Bridge]] pins into high-impedance (the third state) so that we can access the flash without the [[South Bridge]] interfering. | ||
Because the tristate pin is not connected to the [http://www.ps3devwiki.com/index.php?title=Flash_%28Hardware%29#NOR NOR flash] TSOP package, but to the [[South Bridge]] BGA package, this makes tracing the pin quite difficult. One should be able to locate it by having the running you could ground out the unknown pins whilst checking the continuity of a known address or data line against ground. These should enter high-impedance or no-continuity when you ground out SB_DISABLE. | |||
= Board Revisions = | |||
== | == COK-001, COK-002, SEM-001 == | ||
= | These are the earliest revisions of the PS3 motherboard (CECHA, CECHB, CECHC, CECHE, CECHG) and contain 2 x Samsung K9F1G08U0A-PIB0 128MB [http://www.ps3devwiki.com/index.php?title=Flash_%28Hardware%29#NAND NAND Chips] for a total of 256MB. These chips are interleaved which is controlled by a proprietary controller chip codenamed "[[Starship2]]" or SS2. This chip handles the interleaving and presents the [http://www.ps3devwiki.com/index.php?title=Flash_%28Hardware%29#NAND NANDS] to the [[South Bridge]] as a single large coherent NOR Chip. | ||
== DIA-001, DIA-002 == | |||
These boards were the first to get the [http://www.ps3devwiki.com/index.php?title=Flash_%28Hardware%29#NOR NOR flash] memory from the middle revisions of the PS3 (CECHH, CECHJ, CECHK). Only a single Spansion S29GL128N90TFIR2 16MB [http://www.ps3devwiki.com/index.php?title=Flash_%28Hardware%29#NOR NOR flash] chip is used and the [[Starship2]] chip has been completely removed. The 128N is JEDEC CFI compliant and organized as 8,388,608 words or 16,777,216 bytes, addressable as 16-bit words (PS3 modus operandi) and 8-bit / 1 byte when the BYTE# signal is logic zero. | |||
== VER-001 == | |||
Used in the last revisions of the fatter model PS3 (CECHL, CECHM, CECHP, CECHQ), again with the single Spansion S29GL128N90TFIR2 16MB [http://www.ps3devwiki.com/index.php?title=Flash_%28Hardware%29#NOR NOR flash] with the exception of the CECHL which used a Samsung K8Q2815UQB-P14B 16MB [http://www.ps3devwiki.com/index.php?title=Flash_%28Hardware%29#NOR NOR flash]. | |||
== | == JSD-001 == | ||
This is the pinout originally supplied by Marcan for a CECH-2504A, Points match those taken from a CECH-2504B slim console. Most slims may carry this arrangement. | |||
== | = Pinout Gallery = | ||
<Gallery> | <Gallery> | ||
File: | File:SS2_NOR.JPG|SS2 NOR Testpoints | ||
File: | File:VER-001_NOR.JPG|VER-001 NOR Testpoints | ||
File: | File:DIA-001_NOR.JPG|DIA-001 NOR Testpoints | ||
File: | File:DYN-001_NOR.JPG|DYN-001 Testpoints | ||
File: | File:JSD-001_NOR.JPG|JSD-001 Testpoints | ||
File: | File:COK-001-NOR.jpg|COK-001 NOR Testpoints (only overlay) | ||
File: | File:COK-001-NOR_1.jpg|COK-001 NOR Testpoints | ||
</Gallery> | </Gallery> | ||