Editing CXM4024R

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Line 20: Line 20:
| 1 || {{cellcolors|#333|#fff}} AVS ||  
| 1 || {{cellcolors|#333|#fff}} AVS ||  
|-
|-
| 2 || {{cellcolors|#f83|#fff}} VREF2 || Connected to +3.3V_ANA through 2.4K resitor
| 2 || VREF2 ||  
|-
|-
| 3 || {{cellcolors|#333|#fff}} TESTIN ||  
| 3 || {{cellcolors|#333|#fff}} TESTIN ||  
Line 50: Line 50:
| 16 || {{cellcolors|#f66|#fff}} AVCC1 / +5V_ANA ||  
| 16 || {{cellcolors|#f66|#fff}} AVCC1 / +5V_ANA ||  
|-
|-
| 17 || {{cellcolors|#ccc}} S2 || Not Connected
| 17 || S2 ||  
|-
|-
| 18 || {{cellcolors|#ccc}} DL3 || Not Connected
| 18 || DL3 ||  
|-
|-
| 19 || {{cellcolors|#ccc}} DL2 || Not Connected
| 19 || DL2 ||  
|-
|-
| 20 || {{cellcolors|#ccc}} DL1 || Not Connected
| 20 || DL1 ||  
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|-
| 21 || {{cellcolors|#f33|#fff}} DVD / +1.5V_RSX_VDDIO ||  
| 21 || {{cellcolors|#f33|#fff}} DVD / +1.5V_RSX_VDDIO ||  
Line 62: Line 62:
| 22 || {{cellcolors|#333|#fff}} VSS ||  
| 22 || {{cellcolors|#333|#fff}} VSS ||  
|-
|-
| 23 || {{cellcolors|#f83|#fff}} VG1 || Connected to +3.3V_ANA through 0.1uf capacitor
| 23 || VG1 ||  
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|-
| 24 || {{cellcolors|#f83|#fff}} AVD / +3.3V_ANA ||  
| 24 || {{cellcolors|#f83|#fff}} AVD / +3.3V_ANA ||  
Line 70: Line 70:
! colspan="3" style="padding:1px" data-sort-value="25.5"|
! colspan="3" style="padding:1px" data-sort-value="25.5"|
|-
|-
| 26 || {{cellcolors|#f83|#fff}} VREF1 || Connected to +3.3V_ANA through 2.4K resitor
| 26 || VREF1 ||  
|-
|-
| 27 || {{cellcolors|#f83|#fff}} AVD / +3.3V_ANA ||  
| 27 || {{cellcolors|#f83|#fff}} AVD / +3.3V_ANA ||  
Line 80: Line 80:
| 30 || {{cellcolors|#333|#fff}} EXTDAC1 ||  
| 30 || {{cellcolors|#333|#fff}} EXTDAC1 ||  
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|-
| 31 || {{cellcolors|#6666ff|#ffff00}} RESET || <strike>VO_RST1 ? / Connected to [[RSX]] pad AK38 ([[Template:RSX pad layout 41x41|RSX layout 41x41]]) ?</strike> or<br>Connected to [[Syscon Hardware|Syscon]] pad B5 ([[Template:Syscon_pinout_BGA_200_pads|BGA 200 pads layout]])
| 31 || {{cellcolors|#f6f}} RESET || VO_RST0 ? / Connected to [[RSX]] pad AU23 ([[Template:RSX pad layout 41x41|RSX layout 41x41]]) ?
|-
|-
| 32 || {{cellcolors|#f6f}} NTPAL || <strike>NT_PL00 ? / Connected to [[RSX]] pad AU33 ([[Template:RSX pad layout 41x41|RSX layout 41x41]]) ?</strike> or<br>NT_PL01 ? / Connected to [[RSX]] pad AA37 ([[Template:RSX pad layout 41x41|RSX layout 41x41]]) ?
| 32 || {{cellcolors|#f6f}} NTPAL || NT_PL01 ? / Connected to [[RSX]] pad AA37 ([[Template:RSX pad layout 41x41|RSX layout 41x41]]) ?
|-
|-
| 33 || {{cellcolors|#333|#fff}} VSS ||  
| 33 || {{cellcolors|#333|#fff}} VSS ||  
|-
|-
| 34 || {{cellcolors|#f6f}} FLD0 || <strike>FLDO0 ? / Connected to [[RSX]] pad AW22 ([[Template:RSX pad layout 41x41|RSX layout 41x41]]) ?</strike> or<br>FLDO1 ? / Connected to [[RSX]] pad AM40 ([[Template:RSX pad layout 41x41|RSX layout 41x41]]) ?
| 34 || {{cellcolors|#f6f}} FLD0 || FLDO0 ? / Connected to [[RSX]] pad AW22 ([[Template:RSX pad layout 41x41|RSX layout 41x41]]) ?
|-
|-
| 35 || {{cellcolors|#6666ff|#ffff00}} SCL / DVE_I2C_SCL || Connected to [[Syscon Hardware|Syscon]] pad A10 ([[Template:Syscon_pinout_BGA_200_pads|BGA 200 pads layout]]), or pin 121 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]])
| 35 || {{cellcolors|#6666ff|#ffff00}} SCL / DVE_I2C_SCL || Connected to [[Syscon Hardware|Syscon]] pad A10 ([[Template:Syscon_pinout_BGA_200_pads|BGA 200 pads layout]])
|-
|-
| 36 || {{cellcolors|#6666ff|#ffff00}} SDA / DVE_I2C_SDA || Connected to [[Syscon Hardware|Syscon]] pad B10 ([[Template:Syscon_pinout_BGA_200_pads|BGA 200 pads layout]]), or pin 122 ([[Template:Syscon_pinout_LQFP_128_pins|LQFP 128 pins layout]])
| 36 || {{cellcolors|#6666ff|#ffff00}} SDA / DVE_I2C_SDA || Connected to [[Syscon Hardware|Syscon]] pad B10 ([[Template:Syscon_pinout_BGA_200_pads|BGA 200 pads layout]])
|-
|-
| 37 || {{cellcolors|#ff6}} R11 / RSX_VO71 || Connected to [[RSX]] pad AA39 ([[Template:RSX pad layout 41x41|RSX layout 41x41]])
| 37 || {{cellcolors|#ff6}} R11 / RSX_VO71 || Connected to [[RSX]] pad AA39 ([[Template:RSX pad layout 41x41|RSX layout 41x41]])
Line 192: Line 192:
| 84 || {{cellcolors|#f6f}} HSYNC || HSYNC_01 ? / Connected to [[RSX]] pad AK40 ([[Template:RSX pad layout 41x41|RSX layout 41x41]]) ?
| 84 || {{cellcolors|#f6f}} HSYNC || HSYNC_01 ? / Connected to [[RSX]] pad AK40 ([[Template:RSX pad layout 41x41|RSX layout 41x41]]) ?
|-
|-
| 85 || {{cellcolors|#f6f}} DEN || RSX_VO_DE1 ? / Connected to [[RSX]] pad AL40 ([[Template:RSX pad layout 41x41|RSX layout 41x41]]) ?
| 85 || DEN ||  
|-
|-
| 86 || {{cellcolors|#333|#fff}} TMODE1 ||  
| 86 || {{cellcolors|#333|#fff}} TMODE1 ||  
Line 200: Line 200:
| 88 || {{cellcolors|#f33|#fff}} DVD / +1.5V_RSX_VDDIO ||  
| 88 || {{cellcolors|#f33|#fff}} DVD / +1.5V_RSX_VDDIO ||  
|-
|-
| 89 || {{cellcolors|#ccc}} HSYNC0 || Not Connected
| 89 || HSYNC0 ||  
|-
|-
| 90 || {{cellcolors|#ccc}} VSYNCO || Not Connected
| 90 || VSYNCO ||  
|-
|-
| 91 || {{cellcolors|#ccc}} PLLOUT || Not Connected
| 91 || PLLOUT ||  
|-
|-
| 92 || {{cellcolors|#333|#fff}} SCAN_ENABLE ||  
| 92 || {{cellcolors|#333|#fff}} SCAN_ENABLE ||  
|-
|-
| 93 || {{cellcolors|#f6f}} CLOCK || RSX_CLKOUT1 ? / Connected to [[RSX]] pad AE36 ([[Template:RSX pad layout 41x41|RSX layout 41x41]]) ?
| 93 || CLOCK ||  
|-
|-
| 94 || {{cellcolors|#333|#fff}} VSS ||  
| 94 || {{cellcolors|#333|#fff}} VSS ||  
|-
|-
| 95 || {{cellcolors|#333|#fff}} VSSP ||  
| 95 || VSSP ||  
|-
|-
| 96 || {{cellcolors|#f33|#fff}} DVDP / +1.5V_RSX_VDDIO ||  
| 96 || {{cellcolors|#f33|#fff}} DVDP / +1.5V_RSX_VDDIO ||  
Line 220: Line 220:
| 98 || {{cellcolors|#f83|#fff}} AVD / +3.3V_ANA ||  
| 98 || {{cellcolors|#f83|#fff}} AVD / +3.3V_ANA ||  
|-
|-
| 99 || {{cellcolors|#f83|#fff}} VG2 || Connected to +3.3V_ANA through 0.1uf capacitor
| 99 || VG2 ||  
|-
|-
| 100 || {{cellcolors|#f83|#fff}} AVD / +3.3V_ANA ||  
| 100 || {{cellcolors|#f83|#fff}} AVD / +3.3V_ANA ||  
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