Talk:CellBE Hardware Implementation Registers
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Reserved bits HIDx
Guessed[edit source]
These were extracted by guessing what they do from the analyzed code and the values.
4:6 bit should be L1 data cache related (similar to en_dway bits)
HID4[edit source]
| pvr | type | 4:6 bit (3 bits) | en_dway |
|---|---|---|---|
| 0x0000000000700000 | 90nm | 0b011 | 0b0000 |
| 0x0000000000700100 | 90nm | 0b011 | 0b0000 |
| 0x0000000000700101 | 90nm ? | 0b011 | 0b0000 |
| 0x0000000000700400 | ? | none | 0b1111 |
| 0x0000000000700500 | ? | none | 0b1111 |
| 0x0000000000700501 | ? | none | 0b1111 |
pvr < 7.4.0 doesn't use en_dway
Bad wiring?
Unknown[edit source]
These were extracted by guessing what they do from the analyzed code and the values.
HID0[edit source]
| pvr | type | 0:1 bit (2 bits) |
|---|---|---|
| 0x0000000000700000 | 90nm | 0b01 |
| 0x0000000000700100 | 90nm | 0b01 |
| 0x0000000000700101 | 90nm ? | 0b01 |
| 0x0000000000700400 | ? | 0b00 |
| 0x0000000000700500 | ? | 0b00 |
| 0x0000000000700501 | ? | 0b00 |
pvr >= 7.4.0 doesn't use 0:1 bit