CPU: Difference between revisions
(Undo revision 150 by 109.230.216.60 (talk)) |
No edit summary |
||
| (16 intermediate revisions by 5 users not shown) | |||
| Line 1: | Line 1: | ||
[[Category:Hardware]] | [[Category:Hardware]]<noinclude>[[Category:Main]]</noinclude> | ||
== 4 core ARM Cortex-A9 MPCore == | == 4 core ARM Cortex-A9 MPCore == | ||
| Line 7: | Line 7: | ||
* Designed by: ARM | * Designed by: ARM | ||
* Common manufacturer(s): TSMC | * Common manufacturer(s): TSMC | ||
* CPU clock rate: | * CPU clock rate: 111 MHz to 500 MHz (Clockrate can be manually changed if the handheld is modded) | ||
* Instruction set: ARMv7 | * Instruction set: ARMv7 | ||
* Cores: 1-4 | * Cores: 1-4 | ||
* L1 cache: 32 kB I/32 kB D | * L1 cache: 32 kB I/32 kB D | ||
* L2 cache controller: (0-4 MB) | * L2 cache controller: (0-4 MB) | ||
The actual application processor cores are [http://www.arm.com/products/processors/cortex-a/cortex-a9.php Cortex A9], which is common in modern high performance embedded devices like cell phones and tablets. The [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0388i/index.html Technical Reference Manual] gives a good overview of the specific processor features and is a good reference for what ARMv7 implementation specific features are enabled. The Vita cores have a MIDR value of <code>0x412FC09A</code>, meaning it is Cortex A9 r2p10. Indeed there are usage of undocumented CP15 registers. | |||
Another manual that's important is the [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407i/index.html MPCore Technical Reference Manual] which is specific to the multi-core system the Vita uses. The main information of use are descriptors for the private memory region defined with the <code>PERIPHBASE</code> signal. This is mapped to [[Physical Memory|physical address]] <code>0x1A000000</code>. | |||
== Interrupt Controller == | |||
As part of the Cortex A9 MPcore, the Vita also implements the [http://www.systems.ethz.ch/sites/default/files/file/aos2012/ReferenceMaterial/InterruptHandling/GIC_architecture_spec_v1_0.pdf Generic Interrupt Controller Architecture]. More information on interrupts can be found [[Interrupts|here]]. | |||
== PL310 L2 Cache == | |||
The Vita uses the [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246a/index.html PL310] L2 cache is is [[Physical Memory|mapped]] to <code>0x1A002000</code>. | |||
=== Debugging/Tracing === | === Debugging/Tracing === | ||
Latest revision as of 08:37, 23 March 2018
4 core ARM Cortex-A9 MPCore[edit | edit source]
The ARM Cortex-A9 MPCore is a multicore processor providing up to 4 cache-coherent Cortex-A9 cores, each implementing the ARM v7 instruction set architecture.
Specifications[edit | edit source]
- Designed by: ARM
- Common manufacturer(s): TSMC
- CPU clock rate: 111 MHz to 500 MHz (Clockrate can be manually changed if the handheld is modded)
- Instruction set: ARMv7
- Cores: 1-4
- L1 cache: 32 kB I/32 kB D
- L2 cache controller: (0-4 MB)
The actual application processor cores are Cortex A9, which is common in modern high performance embedded devices like cell phones and tablets. The Technical Reference Manual gives a good overview of the specific processor features and is a good reference for what ARMv7 implementation specific features are enabled. The Vita cores have a MIDR value of 0x412FC09A, meaning it is Cortex A9 r2p10. Indeed there are usage of undocumented CP15 registers.
Another manual that's important is the MPCore Technical Reference Manual which is specific to the multi-core system the Vita uses. The main information of use are descriptors for the private memory region defined with the PERIPHBASE signal. This is mapped to physical address 0x1A000000.
Interrupt Controller[edit | edit source]
As part of the Cortex A9 MPcore, the Vita also implements the Generic Interrupt Controller Architecture. More information on interrupts can be found here.
PL310 L2 Cache[edit | edit source]
The Vita uses the PL310 L2 cache is is mapped to 0x1A002000.
Debugging/Tracing[edit | edit source]
CoreSight for Cortex-A series processors enable developers to control (debug) and observe (trace) their Cortex-A processor-based SoC with fewer pins. Cortex-A processor debug and run time control can be performed with only 2 pins using the Serial Wire Debug technology or alternatively using JTAG, when highly compressed real-time trace of the cores and others system trace can be captured on-chip (ETB) or exported through a dedicated trace port (TPIU).