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COP1 is the nomenclature for PSP's CPU Floating | <b>COP1</b> is the nomenclature for PSP's CPU Floating Point Unit, or shortly FPU. | ||
== Specifications == | |||
PSP's COP1 can only operate with 32-bit single precision floating-point numbers, <b>it does not support 64-bit floating-point numbers</b>. | |||
* It has 32 32-bit registers (<code>$f0</code>-<code>$f31</code>). | |||
* It is IEEE 754 compliant. | |||
== Operations execution time == | |||
{| class="wikitable" | |||
! Operation | |||
! Time (in cycles) | |||
|- | |||
| <b>Square root</b> (sqrt) | |||
| <b>28</b> cycles | |||
|- | |||
| <b>Division</b> (div) | |||
| <b>28</b> cycles | |||
|- | |||
| <i>... (most others)</i> | |||
| <b>1</b> cycle | |||
|} | |||
Latest revision as of 16:42, 3 June 2023
COP1 is the nomenclature for PSP's CPU Floating Point Unit, or shortly FPU.
Specifications[edit | edit source]
PSP's COP1 can only operate with 32-bit single precision floating-point numbers, it does not support 64-bit floating-point numbers.
- It has 32 32-bit registers (
$f0-$f31). - It is IEEE 754 compliant.
Operations execution time[edit | edit source]
| Operation | Time (in cycles) |
|---|---|
| Square root (sqrt) | 28 cycles |
| Division (div) | 28 cycles |
| ... (most others) | 1 cycle |