COP2: Difference between revisions

Revision as of 20:30, 3 June 2023

COP2 is the nomenclature for PSP's CPU Vector Floating Point Unit, or shortly VFPU.

Functionality is similar to PS2's VFPU Macromode
It is designed for vector and matrix operations.
It supports some trigonometric functions, binary logarithm, square root, and others.
It has 128 32-bit registers.
Reconfigurable as scalar, vector or matrix.
It can handle these types of numbers:
- 32-bit IEEE 754 floating-point numbers.
- 32-bit integer numbers.
- 16-bit integer numbers.
- 8-bit integer numbers.
- 16-bit floating-point numbers (half-precision float).

Instruction	Operation	Time (in cycles)
`vmmul.q vd, vs, vt`	4×4 matrix multiply	22 cycles

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-COP2 is the nomenclature for PSP's CPU Vector Floating point unit (otherwise known as a VFPU).
+<b>COP2</b> is the nomenclature for PSP's CPU Vector Floating Point Unit, or shortly VFPU.
-'''Specs'''
+== Specifications ==
-   * Vector FPU “Macromode only”
+* Functionality is similar to PS2's VFPU Macromode
-   * Designed for vector and matrix ops
+* It is designed for vector and matrix operations.
-   * 128 32-bit registers
+* It supports some <b>trigonometric functions</b>, <b>binary logarithm</b>, <b>square root</b>, and others.
-         o Reconfigurable as scalar, vector or matrix
+* It has <b>128</b> 32-bit registers.
-         o IEEE 754 Single precision float
+* Reconfigurable as scalar, vector or matrix.
-   * Can also handle 32-bit int, 16-bit int, 8-bit int, half float
+* It can handle these types of numbers:
-   * vmmul.z vd, vs, vt - 4×4 matrix/vector multiply, 22 cycles
+** 32-bit IEEE 754 floating-point numbers.
+** 32-bit integer numbers.
+** 16-bit integer numbers.
+** 8-bit integer numbers.
+** 16-bit floating-point numbers (half-precision float).
+== Instructions ==
+{{caution| small=yes |This table is not completed yet.}}
+{| class=wikitable
+! Instruction
+! Operation
+! Time (in cycles)
+|-
+! <code>vmmul.q vd, vs, vt</code>
+| 4×4 matrix multiply
+| <b>22</b> cycles
+|}