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== | [[Category:Hardware]]<noinclude>[[Category:Main]]</noinclude> | ||
== 4 core ARM Cortex-A9 MPCore == | |||
The ARM Cortex-A9 MPCore is a multicore processor providing up to 4 cache-coherent Cortex-A9 cores, each implementing the ARM v7 instruction set architecture. | |||
=== Specifications === | === Specifications === | ||
* | * Designed by: ARM | ||
* | * Common manufacturer(s): TSMC | ||
* | * CPU clock rate: 800 MHz to 2000 MHz (generic spec, needs confirmation on Vita platform) | ||
* | * Instruction set: ARMv7 | ||
* | * Cores: 1-4 | ||
* | * L1 cache: 32 kB I/32 kB D | ||
** | * L2 cache controller: (0-4 MB) | ||
** | |||
* | The actual application processor cores are [http://www.arm.com/products/processors/cortex-a/cortex-a9.php Cortex A9], which is common in modern high performance embedded devices like cell phones and tablets. The [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0388i/index.html Technical Reference Manual] gives a good overview of the specific processor features and is a good reference for what ARMv7 implementation specific features are enabled. The Vita cores have a MIDR value of <code>0x412FC09A</code>, meaning it is Cortex A9 r2p10. Indeed there are usage of undocumented CP15 registers. | ||
Another manual that's important is the [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407i/index.html MPCore Technical Reference Manual] which is specific to the multi-core system the Vita uses. The main information of use are descriptors for the private memory region defined with the <code>PERIPHBASE</code> signal. This is mapped to [[Physical Memory|physical address]] <code>0x1A000000</code>. | |||
== Interrupt Controller == | |||
As part of the Cortex A9 MPcore, the Vita also implements the [http://www.systems.ethz.ch/sites/default/files/file/aos2012/ReferenceMaterial/InterruptHandling/GIC_architecture_spec_v1_0.pdf Generic Interrupt Controller Architecture]. More information on interrupts can be found [[Interrupts|here]]. | |||
== PL310 L2 Cache == | |||
The Vita uses the [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246a/index.html PL310] L2 cache is is [[Physical Memory|mapped]] to <code>0x1A002000</code>. | |||
=== Debugging/Tracing === | |||
CoreSight for Cortex-A series processors enable developers to control (debug) and observe (trace) their Cortex-A processor-based SoC with fewer pins. Cortex-A processor debug and run time control can be performed with only 2 pins using the Serial Wire Debug technology or alternatively using JTAG, when highly compressed real-time trace of the cores and others system trace can be captured on-chip (ETB) or exported through a dedicated trace port (TPIU). | |||
== External References == | |||
* [http://www.arm.com/products/processors/cortex-a/cortex-a9.php ARM Cortex-A9 Processor - main page] | |||
** [http://www.arm.com/files/pdf/ARMCortexA-9Processors.pdf White paper - The ARM Cortex-A9 Processors] | |||
** [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407e/index.html Cortex-A9 MPCore Technical Reference Manual] | |||
* [http://www.arm.com/products/system-ip/debug-trace/coresight-soc-components/index.php CoreSight - main page] | |||
** [http://www.arm.com/products/system-ip/debug-trace/coresight-soc-components/serial-wire-debug.php CoreSight Debug Access Port : Serial Wire Debug] | |||
Revision as of 00:52, 16 June 2017
4 core ARM Cortex-A9 MPCore
The ARM Cortex-A9 MPCore is a multicore processor providing up to 4 cache-coherent Cortex-A9 cores, each implementing the ARM v7 instruction set architecture.
Specifications
- Designed by: ARM
- Common manufacturer(s): TSMC
- CPU clock rate: 800 MHz to 2000 MHz (generic spec, needs confirmation on Vita platform)
- Instruction set: ARMv7
- Cores: 1-4
- L1 cache: 32 kB I/32 kB D
- L2 cache controller: (0-4 MB)
The actual application processor cores are Cortex A9, which is common in modern high performance embedded devices like cell phones and tablets. The Technical Reference Manual gives a good overview of the specific processor features and is a good reference for what ARMv7 implementation specific features are enabled. The Vita cores have a MIDR value of 0x412FC09A, meaning it is Cortex A9 r2p10. Indeed there are usage of undocumented CP15 registers.
Another manual that's important is the MPCore Technical Reference Manual which is specific to the multi-core system the Vita uses. The main information of use are descriptors for the private memory region defined with the PERIPHBASE signal. This is mapped to physical address 0x1A000000.
Interrupt Controller
As part of the Cortex A9 MPcore, the Vita also implements the Generic Interrupt Controller Architecture. More information on interrupts can be found here.
PL310 L2 Cache
The Vita uses the PL310 L2 cache is is mapped to 0x1A002000.
Debugging/Tracing
CoreSight for Cortex-A series processors enable developers to control (debug) and observe (trace) their Cortex-A processor-based SoC with fewer pins. Cortex-A processor debug and run time control can be performed with only 2 pins using the Serial Wire Debug technology or alternatively using JTAG, when highly compressed real-time trace of the cores and others system trace can be captured on-chip (ETB) or exported through a dedicated trace port (TPIU).