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COP2 is the nomenclature for PSP's CPU Vector Floating | <b>COP2</b> is the nomenclature for PSP's CPU Vector Floating Point Unit, or shortly VFPU. | ||
== Specifications == | |||
* Functionality is similar to PS2's VU0 Macromode, but with less exposed pipeline and without own memory and DMA interface. | |||
* It is designed for vector and matrix operations. | |||
* It supports some <b>trigonometric functions</b>, <b>binary logarithm</b>, <b>square root</b>, and others. | |||
* It has <b>128</b> 32-bit registers, and additional 16(?) 32 bits control registers. | |||
* Reconfigurable as scalar, vector or matrix. | |||
* It can handle these types of numbers: | |||
** 32-bit IEEE 754 floating-point numbers | |||
*** Note: Unit is not fully IEEE 754 compliant. Denormals are treated as zero. Hardcoded nearest rounding mode. Some other not yet reversed math quirks which ends up with different results comparing to IEEE 754. While unit is much closer to IEEE 754 than FPU/VU in PS2, its behavior is still not fully understood. | |||
** 32-bit integer numbers. | |||
** 16-bit integer numbers. | |||
** 8-bit integer numbers. | |||
** 16-bit floating-point numbers (half-precision float). | |||
== Instructions == | |||
{{caution| small=yes |This table is not completed yet.}} | |||
{| class=wikitable | |||
! Instruction | |||
! Operation | |||
! Time (in cycles) | |||
|- | |||
! <code>vmmul.q vd, vs, vt</code> | |||
| 4×4 matrix multiply | |||
| <b>22</b> cycles | |||
|} | |||
== See also == | |||
* [https://pspdev.github.io/vfpu-docs/ VFPU documentation by davidgfnet] | |||
Latest revision as of 14:22, 21 January 2024
COP2 is the nomenclature for PSP's CPU Vector Floating Point Unit, or shortly VFPU.
Specifications[edit | edit source]
- Functionality is similar to PS2's VU0 Macromode, but with less exposed pipeline and without own memory and DMA interface.
- It is designed for vector and matrix operations.
- It supports some trigonometric functions, binary logarithm, square root, and others.
- It has 128 32-bit registers, and additional 16(?) 32 bits control registers.
- Reconfigurable as scalar, vector or matrix.
- It can handle these types of numbers:
- 32-bit IEEE 754 floating-point numbers
- Note: Unit is not fully IEEE 754 compliant. Denormals are treated as zero. Hardcoded nearest rounding mode. Some other not yet reversed math quirks which ends up with different results comparing to IEEE 754. While unit is much closer to IEEE 754 than FPU/VU in PS2, its behavior is still not fully understood.
- 32-bit integer numbers.
- 16-bit integer numbers.
- 8-bit integer numbers.
- 16-bit floating-point numbers (half-precision float).
- 32-bit IEEE 754 floating-point numbers
Instructions[edit | edit source]
 |
This table is not completed yet. |
| Instruction | Operation | Time (in cycles) |
|---|---|---|
vmmul.q vd, vs, vt
|
4×4 matrix multiply | 22 cycles |