Tachyon: Difference between revisions
CelesteBlue (talk | contribs) No edit summary |
CelesteBlue (talk | contribs) No edit summary |
||
| Line 1: | Line 1: | ||
Tachyon is the codename of the chip which contains the CPU, ME and | Tachyon is the codename of the chip which contains the CPU, ME, GE and maybe also VME. Tachyon has one primary CPU core which is responsible for running the XMB and games, and a second CPU core which implements the audio and video decoding functionality of the PSP. | ||
[[File:PSP CXD2962GG.jpg|thumb|left|PSP CXD2962GG]]<br> | [[File:PSP CXD2962GG.jpg|thumb|left|PSP CXD2962GG]]<br> | ||
| Line 17: | Line 17: | ||
<br> | <br> | ||
== | == Main Core "SC" == | ||
The PSP's CPU is a dual core 32-bit Little Endian MIPS based on the R4000 design with a few custom instructions. | The PSP's CPU is a dual core 32-bit Little Endian MIPS based on the R4000 design with a few custom instructions. | ||
Both CPU cores have their own 16 KiB Instruction and 16KiB Data caches. | Both CPU cores have their own 16 KiB Instruction and 16KiB Data caches. The main CPU has an internal 16 KiB of scratchpad RAM that is accessed directly without going through the system bus. | ||
The CPU | |||
The main CPU has three coprocessors: | The main CPU has three coprocessors: | ||
| Line 34: | Line 28: | ||
*COP2 - Vector Floating Point Unit (up to 3.2 GFLOPS) | *COP2 - Vector Floating Point Unit (up to 3.2 GFLOPS) | ||
The main | The CPU defaults to 222MHz, but can be configured to run from 1-333 MHz. | ||
The CPU cores are connected to main memory and other peripherals like the Graphics Engine through a system bus that is limited to 1/2 of the CPU's configured clock speed. | |||
== | == Media Engine == | ||
The | The Media Engine ("ME") is a second MIPS based CPU core that was not directly accessible by licensed developers. Instead, Sony runs code on the ME to facilitate decoding audio and video assets, along with the help of more specialized hardware like the Virtual Mobile Engine and "AVC". | ||
The ME runs at the same clock frequency as the main CPU core. | The ME runs at the same clock frequency as the main CPU core. | ||
| Line 46: | Line 42: | ||
*COP1 - 32-bit Floating Point Unit | *COP1 - 32-bit Floating Point Unit | ||
The | == Graphics Engine == | ||
== Virtual Mobile Engine == | |||
The VME appears to be one half of Sony's "Virtual Mobile Engine Concept 2" where a CPU would take care of "lightweight control tasks" and reconfigurable hardware logic (the VME) would do all of the "heavy work in a power efficient manner". See [https://www.yumpu.com/en/document/read/10961029/virtual-mobile-enginetm-vme-sony Virtual Mobile Engine - LSI that "Changes its Spots"]. | |||
== Versions == | == Versions == | ||
| Line 54: | Line 54: | ||
*CPU and DDR are discrete ICs on the motherboard | *CPU and DDR are discrete ICs on the motherboard | ||
*32 MiB main memory (DDR) | *32 MiB main memory (DDR) | ||
*2 MiB Media Engine memory (eDRAM) | *2 MiB Media Engine memory (eDRAM) | ||
| Line 61: | Line 60: | ||
*DDR is brought into the CPU's package | *DDR is brought into the CPU's package | ||
*64 MiB main memory (DDR) | *64 MiB main memory (DDR) | ||
*4 MiB Media Engine memory (eDRAM) | *4 MiB Media Engine memory (eDRAM) | ||
== See also == | |||
* https://www.zdnet.com/article/sony-reveals-some-specs-for-psp-handheld/ (2004) | |||
https://www.extremetech.com/extreme/56942-sony-details-psp-chip-specs | |||
https://www.copetti.org/writings/consoles/playstation-portable/ | |||
Revision as of 14:43, 9 February 2022
Tachyon is the codename of the chip which contains the CPU, ME, GE and maybe also VME. Tachyon has one primary CPU core which is responsible for running the XMB and games, and a second CPU core which implements the audio and video decoding functionality of the PSP.
Main Core "SC"
The PSP's CPU is a dual core 32-bit Little Endian MIPS based on the R4000 design with a few custom instructions.
Both CPU cores have their own 16 KiB Instruction and 16KiB Data caches. The main CPU has an internal 16 KiB of scratchpad RAM that is accessed directly without going through the system bus.
The main CPU has three coprocessors:
- COP0 - general system control
- COP1 - 32-bit Floating Point Unit
- COP2 - Vector Floating Point Unit (up to 3.2 GFLOPS)
The CPU defaults to 222MHz, but can be configured to run from 1-333 MHz.
The CPU cores are connected to main memory and other peripherals like the Graphics Engine through a system bus that is limited to 1/2 of the CPU's configured clock speed.
Media Engine
The Media Engine ("ME") is a second MIPS based CPU core that was not directly accessible by licensed developers. Instead, Sony runs code on the ME to facilitate decoding audio and video assets, along with the help of more specialized hardware like the Virtual Mobile Engine and "AVC".
The ME runs at the same clock frequency as the main CPU core.
The ME has two co-processors:
- COP0 - general system control
- COP1 - 32-bit Floating Point Unit
Graphics Engine
Virtual Mobile Engine
The VME appears to be one half of Sony's "Virtual Mobile Engine Concept 2" where a CPU would take care of "lightweight control tasks" and reconfigurable hardware logic (the VME) would do all of the "heavy work in a power efficient manner". See Virtual Mobile Engine - LSI that "Changes its Spots".
Versions
PSP-1000
- CPU and DDR are discrete ICs on the motherboard
- 32 MiB main memory (DDR)
- 2 MiB Media Engine memory (eDRAM)
PSP-2000 and later
- DDR is brought into the CPU's package
- 64 MiB main memory (DDR)
- 4 MiB Media Engine memory (eDRAM)
See also
https://www.extremetech.com/extreme/56942-sony-details-psp-chip-specs
https://www.copetti.org/writings/consoles/playstation-portable/