Editing Hardware Registers
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= Introduction = | = Introduction = | ||
On the PSP, except interruptions, almost all the interaction with the hardware is done through memory accesses to "hardware registers" located at the 0xBC000000~0xBFFFFFFF range (actually 0x1C000000~0x1FFFFFFF to which we add the 0x4 uncached flag and the 0x8 kernel flag). Which is the reason why documenting this is vital to understand the PSP hardware. | |||
= 0xA7F00000: L2 cache = | = 0xA7F00000: L2 cache = | ||
Line 451: | Line 451: | ||
Bits 6-11 = UART 0-5 | Bits 6-11 = UART 0-5 | ||
Bits 12-15 = APB ( | Bits 12-15 = APB (?) 0-3 | ||
Bits 16-17 = Audio 0-1 | Bits 16-17 = Audio 0-1 | ||
Bits | Bits 19-21 = ? | ||
Bit 22 = SIRCS (?) | |||
Bit 22 = SIRCS ( | |||
Bit 23 = GPIO | Bit 23 = GPIO | ||
Line 498: | Line 492: | ||
| 0xBC100064 || 4 || RW || SPI clock select | | 0xBC100064 || 4 || RW || SPI clock select | ||
|- | |- | ||
| 0xBC100068 || 4 || RW || | | 0xBC100068 || 4 || RW || 0xF - PLL get/set out select (PLL frequency?) | ||
|- | |- | ||
| 0xBC100070 || 4 || RW || Set Avc power | | 0xBC100070 || 4 || RW || Set Avc power | ||
Line 506: | Line 498: | ||
| 0xBC100074 || 4 || RW || Unknown | | 0xBC100074 || 4 || RW || Unknown | ||
|- | |- | ||
| 0xBC100078 || 4 || RW || I/O enable | | 0xBC100078 || 4 || RW || I/O enable (?) (TODO: verify indices) | ||
Bit 0 = NAND | |||
Bit | Bit 1 = USB | ||
Bit | Bit 2 = ATA | ||
Bits 3-4 = Memstick Interface | |||
Bit | Bit 5 = LCDC | ||
Bit | Bit 6-7 = Audio | ||
Bit | Bit 8 = IIC | ||
Bit | Bit 9 = SIRCS | ||
Bit 10 = Audio? | |||
Bit 11 = KEY | |||
Bit 12 = PWM | |||
Bits | Bits 13-18 = UART | ||
Bits 19-24 = SPI | |||
|- | |- | ||
| 0xBC10007C || 4 || RW || Either GPIO pin enable, or GPIO pin direction | | 0xBC10007C || 4 || RW || Either GPIO pin enable, or GPIO pin direction | ||
Line 873: | Line 856: | ||
|- | |- | ||
|} | |} | ||
= 0xBC700000: ? = | |||
= 0xBC800000: DMACPlus = | = 0xBC800000: DMACPlus = | ||
Line 1,703: | Line 1,688: | ||
| 0xBDE00008 || 4 || RW || Set to 1 on error by the command subroutine | | 0xBDE00008 || 4 || RW || Set to 1 on error by the command subroutine | ||
|- | |- | ||
| 0xBDE0000C || 4 || RW || Set to 1 to start processing | | 0xBDE0000C || 4 || RW || Set to 1 to start processing | ||
|- | |- | ||
| 0xBDE00010 || 4 || RW || KIRK command | | 0xBDE00010 || 4 || RW || KIRK command | ||
Line 1,928: | Line 1,913: | ||
|- | |- | ||
| 0xBE0000D0 || 4 || ? || ?? | | 0xBE0000D0 || 4 || ? || ?? | ||
|- | |||
|} | |} | ||
= 0xBE100000: MagicGate | = 0xBE100000: MagicGate hardware for memory stick? = | ||
= 0xBE140000: LCDC = | |||
{| class="wikitable" | {| class="wikitable" | ||
Line 1,939: | Line 1,927: | ||
! Description | ! Description | ||
|- | |- | ||
| | | 0xBE140000 || 4 || RW || First LCDC controller enable | ||
Bits 0-1 = 3 to enable first LCDC controller (tachyon version < 0x800000; otherwise it's set to 0) | |||
|- | |||
| 0xBE140004 || 4 || RW || Synchronization difference: (xsync / zoom) - ysync | |||
|- | |- | ||
| | | 0xBE140008 || 4 || RW || Unknown (fourth argument of sceLcdcCheckMode and sceLcdcSetMode) | ||
|- | |- | ||
| | | 0xBE140010 || 4 || RW || X back porch | ||
|- | |- | ||
| | | 0xBE140014 || 4 || RW || X sync width | ||
|- | |- | ||
| | | 0xBE140018 || 4 || RW || X front porch | ||
|- | |- | ||
| | | 0xBE14001C || 4 || RW || X resolution | ||
|- | |- | ||
| | | 0xBE140020 || 4 || RW || Y back porch | ||
|- | |- | ||
| | | 0xBE140024 || 4 || RW || Y sync width | ||
|- | |- | ||
| | | 0xBE140028 || 4 || RW || Y front porch | ||
|- | |- | ||
| | | 0xBE14002C || 4 || RW || Y resolution | ||
|- | |- | ||
| | | 0xBE140030 || 4 || R || HPC (?), returned by sceLcdcReadHPC() | ||
|- | |- | ||
| | | 0xBE140034 || 4 || R || VPC (?), returned by sceLcdcReadVPC() | ||
|- | |- | ||
| 0xBE140040 || 4 || RW || Y shift (between hardware & software resolution) | |||
| 0xBE140040 || 4 || RW || Y shift (between hardware & software resolution) | |||
|- | |- | ||
| 0xBE140044 || 4 || RW || X shift (between hardware & software resolution) | | 0xBE140044 || 4 || RW || X shift (between hardware & software resolution) | ||
Line 2,111: | Line 2,061: | ||
| 0xBE240018 || 4 || RW || Is rising edge (?) | | 0xBE240018 || 4 || RW || Is rising edge (?) | ||
|- | |- | ||
| 0xBE24001C || 4 || RW || | | 0xBE24001C || 4 || RW || Is interrupt enabled | ||
|- | |- | ||
| 0xBE240020 || 4 || R? || | | 0xBE240020 || 4 || R? || Is interrupt triggered | ||
|- | |- | ||
| 0xBE240024 || 4 || W || Acknowledge interrupt | | 0xBE240024 || 4 || W || Acknowledge interrupt | ||
|- | |- | ||
| 0xBE240030 || 4 || RW || | | 0xBE240030 || 4 || RW || Is capture port (?) | ||
|- | |- | ||
| 0xBD240034 || 4 || RW || | | 0xBD240034 || 4 || RW || Is timer capture enabled (?) | ||
|- | |- | ||
| 0xBE240040 || 4 || RW || Is input on (?) | | 0xBE240040 || 4 || RW || Is input on (?) | ||
Line 2,132: | Line 2,082: | ||
= 0xBE4C0000 & 0xBE500000: UART = | = 0xBE4C0000 & 0xBE500000: UART = | ||
There are two similar UART controllers: | There are two similar UART controllers: | ||
Line 2,185: | Line 2,133: | ||
= 0xBE580000: Syscon = | = 0xBE580000: Syscon = | ||
{| class="wikitable" | {| class="wikitable" | ||
Line 2,251: | Line 2,196: | ||
|} | |} | ||
= | = 0xBE600000: ? = | ||
= 0xBE700000: Display = | |||
= 0xBFC00000: MIPS Reset Vector = | |||
= 0xBFF00000: NAND DMA buffer = | = 0xBFF00000: NAND DMA buffer = | ||
Line 2,320: | Line 2,221: | ||
= References = | = References = | ||
* [http://daifukkat.su/docs/psptek/ PSPTEK] | * [http://daifukkat.su/docs/psptek/ PSPTEK] (done) | ||
* [https://gigawiz.github.io/yapspd/html_chapters_split/chap8.html yapspd] | * [https://gigawiz.github.io/yapspd/html_chapters_split/chap8.html yapspd] (done) | ||
* [https://github.com/uofw/uofw uOFW] | * [https://github.com/uofw/uofw uOFW] (todo: some more info to grab in some modules) | ||
* [https://github.com/jpcsp/jpcsp Jpcsp] | * [https://github.com/jpcsp/jpcsp Jpcsp] (todo: contains a lot of stuff) |