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== Specifications ==
== Specifications ==
* Functionality is similar to PS2's VU0 Macromode, but with less exposed pipeline and without own memory and DMA interface.
* Functionality is similar to PS2's VFPU Macromode
* It is designed for vector and matrix operations.
* It is designed for vector and matrix operations.
* It supports some <b>trigonometric functions</b>, <b>binary logarithm</b>, <b>square root</b>, and others.
* It supports some <b>trigonometric functions</b>, <b>binary logarithm</b>, <b>square root</b>, and others.
* It has <b>128</b> 32-bit registers, and additional 16(?) 32 bits control registers.
* It has <b>128</b> 32-bit registers.
* Reconfigurable as scalar, vector or matrix.
* Reconfigurable as scalar, vector or matrix.
* It can handle these types of numbers:
* It can handle these types of numbers:
** 32-bit IEEE 754 floating-point numbers  
** 32-bit IEEE 754 floating-point numbers.
*** Note: Unit is not fully IEEE 754 compliant. Denormals are treated as zero. Hardcoded nearest rounding mode. Some other not yet reversed math quirks which ends up with different results comparing to IEEE 754. While unit is much closer to IEEE 754 than FPU/VU in PS2, its behavior is still not fully understood.
** 32-bit integer numbers.
** 32-bit integer numbers.
** 16-bit integer numbers.
** 16-bit integer numbers.
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| 4×4 matrix multiply
| 4×4 matrix multiply
| <b>22</b> cycles
| <b>22</b> cycles
|}
|}
== See also ==
* [https://pspdev.github.io/vfpu-docs/ VFPU documentation by davidgfnet]
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