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<b>COP2</b> is the nomenclature for PSP's CPU Vector Floating Point Unit, or shortly VFPU.
COP2 is the nomenclature for PSP's CPU Vector Floating point unit (otherwise known as a VFPU).


== Specifications ==
'''Specs'''
* Functionality is similar to PS2's VU0 Macromode, but with less exposed pipeline and without own memory and DMA interface.
  * Vector FPU “Macromode only”
* It is designed for vector and matrix operations.
  * Designed for vector and matrix ops
* It supports some <b>trigonometric functions</b>, <b>binary logarithm</b>, <b>square root</b>, and others.
  * 128 32-bit registers
* It has <b>128</b> 32-bit registers, and additional 16(?) 32 bits control registers.
        o Reconfigurable as scalar, vector or matrix
* Reconfigurable as scalar, vector or matrix.
        o IEEE 754 Single precision float
* It can handle these types of numbers:
  * Can also handle 32-bit int, 16-bit int, 8-bit int, half float
** 32-bit IEEE 754 floating-point numbers
  * vmmul.z vd, vs, vt - 4×4 matrix/vector multiply, 22 cycles
*** Note: Unit is not fully IEEE 754 compliant. Denormals are treated as zero. Hardcoded nearest rounding mode. Some other not yet reversed math quirks which ends up with different results comparing to IEEE 754. While unit is much closer to IEEE 754 than FPU/VU in PS2, its behavior is still not fully understood.
** 32-bit integer numbers.
** 16-bit integer numbers.
** 8-bit integer numbers.
** 16-bit floating-point numbers (half-precision float).
 
== Instructions ==
{{caution| small=yes |This table is not completed yet.}}
{| class=wikitable
! Instruction
! Operation
! Time (in cycles)
|-
! <code>vmmul.q vd, vs, vt</code>
| 4×4 matrix multiply
| <b>22</b> cycles
|}
 
== See also ==
* [https://pspdev.github.io/vfpu-docs/ VFPU documentation by davidgfnet]
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