Editing Allegrex

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-The PSP's CPU, named <b>Allegrex</b> — is a dual core 32-bit Little Endian MIPS processor, based on the R4000 design with a few custom instructions.
+Allegrex is the main CPU of the PSP.
-Both CPU cores have their own 16 KiB Instruction and 16 KiB Data caches. The main CPU has an internal 16 KiB of scratchpad RAM, that is accessed directly without going through the system bus.
-The main CPU has three coprocessors:
-* <b>COP0</b>: general system control
-* <b>[[COP1]]</b>: 32-bit Floating Point Unit
-* <b>[[COP2]]</b>: Vector Floating Point Unit (up to 3.2 GFLOPS)
-It has some instructions from <b>MIPS IV:</b> <code>ext, ins, wsbw, seb, seh, rotr, rot(r)v, bitrev, clz, clo</code>.
-It does not seem to have:
-* 64-bit instructions (of course)
-* <code>ll, ldc1, ldc2, lwc2, sc, sdc1, sdc2, swc2</code> (<i>some of them are actually replaced by VFPU instructions with different names</i>)
-* T* (<i>trap and TLB</i>) instructions
-*<code>bltzal, bgezal, bltzall, bgezall</code>
-It also has its own instructions:
-* <code>halt</code> (<i>opcode 0x70000000</i>): This instructions waits for an interruption to wake it up.
-* <code>mfic</code> (<i>opcode 0x70000024 with mask 0xFFFF07FF</i>): It retrieves the interrupt controller state (<i>1: interruptions enabled, 0: interruptions disabled</i>) into the register described by mask 0x0000F800.
-* <code>mtic</code> (<i>opcode 0x70000026 with mask 0xFFFF07FF</i>): It sets the interrupt controller state to the value which is in the register described by mask 0x0000F800.
-The CPU defaults to 222 MHz, but can be configured to run from 1-333 MHz.
-The CPU cores are connected to main memory and other peripherals like the Graphics Engine through a system bus, that is limited to half of the CPU's configured clock speed.
-Since the PSP doesn't have a MMU, the COP0 registers related to TLBs are unused. The PSP also uses the obscure instructions <code>cfc0</code>/<code>ctc0</code> to access "control registers" which are used by the PSP firmware to store various low level data.
-=== Calling convention ===
-The PSP calling convention seems a bit non-standard:
-*<b>Arguments are passed</b> through following registers: <code>$a0, $a1, $a2, $a3, $t0, $t1, $t2, $t3</code>, then on the stack
-*Registers <code>$s0, $s1, $s2, $s3, $s4, $s5, $s6, $s7, $fp</code> (<i>used as a normal registers</i>), <code>$ra</code> (<i>return address</i>), <code>$sp</code> (<i>stack pointer</i>) <b>are saved</b> (<i>or restored</i>) by the callee
-*Registers <code>$t4, $t5, $t6, $t7, $t8, $t9</code> are temporary registers, <b>not saved</b> by the callee
-*Registers <code>$v0, $v1</code> contain the <b>return value</b> of a function: <code>$v0</code> for the lower 32-bits and <code>$v1</code> for the higher 32-bits (if appliable)
-Some registers are used only by the kernel:
-*<code>$gp</code> and <code>$k0</code> are used in only a few specific places in the kernel
-*<code>$k1</code> <b>is used to check permissions</b>: each time an user function is called, it shifts <code>$k1</code> left by 11 bits. The function is in user mode if the <code>$k1</code> value has then its first (highest value) bit set. In then checks either if a pointer has its higher bit set, and/or if its end has its higher bit set, and/or if its size has its higher bit set. If one of those bits is set and we're in user mode, the function returns an error (if it checked the pointer/buffer, which is not always the case).
-*<code>$at</code> (<i>assembly temporary</i>) <b>is used as a temporary register</b>, for hardware manipulation sometimes (to store the hardware register address when reading/writing from/to it).

Editing Allegrex

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