Pinout[edit | edit source]

There are six chips, each with identical inputs but assigned to different channels.

The first chip operates on channels 0 and 1, the second on channels 2 and 3, and so forth.


Pad	Internal Name	External Name	Description
A1	NC_A1
A2	NC_A2
A3	NC_A3
A4	NC_A4
A10	NC_A10
A11	NC_A11
A12	NC_A12
A13	NC_A13
B1	NC_B1
B2	NC_B2
B3	NC_B3
B4	NC_B4
B10	NC_B10
B11	NC_B11
B12	NC_B12
B13	NC_B13
C1	NU_C1
C2	NU_C2
C3	NU_C3
C4	NU_C4
C10	NU_C10
C11	NU_C11
C12	NU_C12
C13	NU_C13
D1	NU_D1
D2	NU_D2
D3	VCCQ_D3	1.2V_FC_VDDQFIO
D4	VCCQ_D4	1.2V_FC_VDDQFIO
D5	DQ1[3]	S50_NAND_CH0_AD3
D6	VSS_D6	GND	Ground
D8	VCC_D8	2.5V_NAND_VCC
D9	DQ1[4]	S50_NAND_CH0_AD4
D10	VCCQ_D10	1.2V_FC_VDDQFIO
D11	VCCQ_D11	1.2V_FC_VDDQFIO
D12	NU_D12
D13	NU_D13
E1	NU_E1
E2	NU_E2
E3	VSSQ_E3	GND	Ground
E4	DQ1[2]	S50_NAND_CH0_AD2
E5	VSSQ_E5	GND	Ground
E6	DQS_1_T	D90_NAND_CH0_DQS_P
E8	RE_1_T	D90_NAND_CH0_RE_P
E9	VSSQ_E9	GND	Ground
E10	DQ1[5]	S50_NAND_CH0_AD5
E11	VSSQ_E11	GND	Ground
E12	NU_E12
E13	NU_E13
F3	DQ1[0]	S50_NAND_CH0_AD0
F4	DQ1[1]	S50_NAND_CH0_AD1
F5	DQS_1_C	D90_NAND_CH0_DQS_N
F6	RE_1_C	D90_NAND_CH0_RE_N
F8	WE_1_N	S50_/NAND_CH0_CE0_WE
F9	VREF_1	1.2V_FC_VDDQFIO
F10	DQ1[6]	S50_NAND_CH0_AD6
F11	DQ1[7]	S50_NAND_CH0_AD7
G3	VSSQ_G3	GND	Ground
G4	VCCQ_G4	1.2V_FC_VDDQFIO
G5	ALE_1	S50_NAND_CH0_ALE
G6	CLE_1	S50_NAND_CH0_CLE
G8	CE3_1_N
G9	CE2_1_N
G10	VCCQ_G10	1.2V_FC_VDDQFIO
G11	VSSQ_G11	GND	Ground
H3	NU_H3
H4	NU_H4
H5	WP_1_N	S50_/NAND_WP
H6	NU_H6
H8	CE1_1_N	S50_/NAND_CH0_CE1
H9	CE0_1_N	S50_/NAND_CH0_CE0
H10	RZQ_1	GND	Ground
H11	NU_H11
J3	VSS_J3	GND	Ground
J4	VCC_J4	2.5V_NAND_VCC
J5	R/B0_0_N	1.2V_FC_VDDQFIO
J6	R/B1_0_N	1.2V_FC_VDDQFIO
J8	R/B1_1_N	1.2V_FC_VDDQFIO
J9	R/B0_1_N	1.2V_FC_VDDQFIO
J10	VCC_J10	2.5V_NAND_VCC
J11	VSS_J11	GND	Ground
K3	NU_K3
K4	RZQ_0	GND	Ground
K5	CE0_0_N	S50_NAND_CH1_CE0
K6	CE1_0_N	S50_NAND_CH1_CE1
K8	VPP
K9	WP_0_N	S50_/NAND_WP
K10	NU_K10
K11	NU_K11
L3	VSSQ_L3	GND	Ground
L4	VCCQ_L4	1.2V_FC_VDDQFIO
L5	CE2_0_N
L6	CE3_0_N
L8	CLE_0	S50_NAND_CH1_CLE
L9	ALE_0	S50_NAND_CH1_ALE
L10	VCCQ_L10	1.2V_FC_VDDQFIO
L11	VSSQ_L11	GND	Ground
M3	DQ0[7]	S50_NAND_CH1_AD7
M4	DQ0[6]	S50_NAND_CH1_AD6
M5	VREF_0	1.2V_FC_VDDQFIO
M6	WE_0_N	S50_NAND_CH1_WE
M8	RE_0_C	D90_NAND_CH1_RE_N
M9	DQS_0_C	D50_NAND_CH1_DQS_N
M10	DQ0[1]	S50_NAND_CH1_AD1
M11	DQ0[0]	S50_NAND_CH1_AD0
N1	NU_N1
N2	NU_N2
N3	VSSQ_N3	GND	Ground
N4	DQ0[5]	S50_NAND_CH1_AD5
N5	VSSQ_N5	GND	Ground
N6	RE_0_T	D90_NAND_CH1_RE_P
N8	DQS_0_T	D50_NAND_CH1_DQS_P
N9	VSSQ_N9	GND	Ground
N10	DQ0[2]	S50_NAND_CH1_AD2
N11	VSSQ_N11	GND	Ground
N12	NU_N12
N13	NU_N13
P1	NU_P1
P2	NU_P2
P3	VCCQ_P3	1.2V_FC_VDDQFIO
P4	VCCQ_P4	1.2V_FC_VDDQFIO
P5	DQ0[4]	S50_NAND_CH1_AD4
P6	VCC_P6	2.5V_NAND_VCC
P8	VSS_P8
P9	DQ0[3]	S50_NAND_CH1_AD3
P10	VCCQ_P10	1.2V_FC_VDDQFIO
P11	VCCQ_P11	1.2V_FC_VDDQFIO
P12	NU_P12
P13	NU_P13
R1	NU_R1
R2	NU_R2
R3	NU_R3
R4	NU_R4
R10	NU_R10
R11	NU_R11
R12	NU_R12
R13	NU_R13
T1	NC_T1
T2	NC_T2
T3	NC_T3
T4	NC_T4
T10	NC_T10
T11	NC_T11
T12	NC_T12
T13	NC_T13
U1	NC_U1
U2	NC_U2
U3	NC_U3
U4	NC_U4
U10	NC_U10
U11	NC_U11
U12	NC_U12
U13	NC_U13