K4A4G085WF-BCTD: Difference between revisions
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(→Pinout: Added K4A4G085WF-BCTD) |
(→Pinout: Added description) |
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| Line 13: | Line 13: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|A2 | |A2 | ||
| Line 19: | Line 19: | ||
|GND | |GND | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
|Ground | |DQ Ground | ||
|- | |- | ||
|A3 | |A3 | ||
| Line 25: | Line 25: | ||
| | | | ||
|[[File:Pin-nc.png|alt=Not connected|frameless]] | |[[File:Pin-nc.png|alt=Not connected|frameless]] | ||
| | |Termination Data Strobe | ||
|- | |- | ||
|A7 | |A7 | ||
| Line 31: | Line 31: | ||
|S50_FC_DDR_DM | |S50_FC_DDR_DM | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Input Data Mask and Data Bus Inversion | ||
|- | |- | ||
|A8 | |A8 | ||
| Line 37: | Line 37: | ||
|GND | |GND | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
|Ground | |DQ Ground | ||
|- | |- | ||
|A9 | |A9 | ||
| Line 49: | Line 49: | ||
|2.5V_DDR4_VPP | |2.5V_DDR4_VPP | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |DRAM Activation Power Supply: 2.5V (2.375V min , 2.75 max) | ||
|- | |- | ||
|B2 | |B2 | ||
| Line 55: | Line 55: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |DQ Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|B3 | |B3 | ||
| Line 61: | Line 61: | ||
|D90_FC_DDR_DQS0_N | |D90_FC_DDR_DQS0_N | ||
|[[File:IC-Pin-Out.png|alt=Others|frameless]] | |[[File:IC-Pin-Out.png|alt=Others|frameless]] | ||
| | |Data Strobe | ||
|- | |- | ||
|B7 | |B7 | ||
| Line 67: | Line 67: | ||
|S50_FC_DDR_D0 | |S50_FC_DDR_D0 | ||
|[[File:IC-Pin-Out.png|alt=Others|frameless]] | |[[File:IC-Pin-Out.png|alt=Others|frameless]] | ||
| | |Data Input/ Output | ||
|- | |- | ||
|B8 | |B8 | ||
| Line 73: | Line 73: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |DQ Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|B9 | |B9 | ||
| Line 79: | Line 79: | ||
|GND | |GND | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Reference Pin for ZQ calibration | ||
|- | |- | ||
|C1 | |C1 | ||
| Line 85: | Line 85: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |DQ Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|C2 | |C2 | ||
| Line 91: | Line 91: | ||
|S50_FC_DDR_D3 | |S50_FC_DDR_D3 | ||
|[[File:IC-Pin-Out.png|alt=Others|frameless]] | |[[File:IC-Pin-Out.png|alt=Others|frameless]] | ||
| | |Data Input/ Output | ||
|- | |- | ||
|C3 | |C3 | ||
| Line 97: | Line 97: | ||
|D90_FC_DDR_DQS0_P | |D90_FC_DDR_DQS0_P | ||
|[[File:IC-Pin-Out.png|alt=Others|frameless]] | |[[File:IC-Pin-Out.png|alt=Others|frameless]] | ||
| | |Data Strobe | ||
|- | |- | ||
|C7 | |C7 | ||
| Line 103: | Line 103: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|C8 | |C8 | ||
| Line 115: | Line 115: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |DQ Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|D1 | |D1 | ||
| Line 121: | Line 121: | ||
|GND | |GND | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
|Ground | |DQ Ground | ||
|- | |- | ||
|D2 | |D2 | ||
| Line 127: | Line 127: | ||
|S50_FC_DDR_D4 | |S50_FC_DDR_D4 | ||
|[[File:IC-Pin-Out.png|alt=Others|frameless]] | |[[File:IC-Pin-Out.png|alt=Others|frameless]] | ||
| | |Data Input/ Output | ||
|- | |- | ||
|D3 | |D3 | ||
| Line 133: | Line 133: | ||
|S50_FC_DDR_D5 | |S50_FC_DDR_D5 | ||
|[[File:IC-Pin-Out.png|alt=Others|frameless]] | |[[File:IC-Pin-Out.png|alt=Others|frameless]] | ||
| | |Data Input/ Output | ||
|- | |- | ||
|D7 | |D7 | ||
| Line 139: | Line 139: | ||
|S50_FC_DDR_D2 | |S50_FC_DDR_D2 | ||
|[[File:IC-Pin-Out.png|alt=Others|frameless]] | |[[File:IC-Pin-Out.png|alt=Others|frameless]] | ||
| | |Data Input/ Output | ||
|- | |- | ||
|D8 | |D8 | ||
| Line 145: | Line 145: | ||
|S50_FC_DDR_D1 | |S50_FC_DDR_D1 | ||
|[[File:IC-Pin-Out.png|alt=Others|frameless]] | |[[File:IC-Pin-Out.png|alt=Others|frameless]] | ||
| | |Data Input/ Output | ||
|- | |- | ||
|D9 | |D9 | ||
| Line 151: | Line 151: | ||
|GND | |GND | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
|Ground | |DQ Ground | ||
|- | |- | ||
|E1 | |E1 | ||
| Line 163: | Line 163: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |DQ Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|E3 | |E3 | ||
| Line 169: | Line 169: | ||
|S50_FC_DDR_D6 | |S50_FC_DDR_D6 | ||
|[[File:IC-Pin-Out.png|alt=Others|frameless]] | |[[File:IC-Pin-Out.png|alt=Others|frameless]] | ||
| | |Data Input/ Output | ||
|- | |- | ||
|E7 | |E7 | ||
| Line 175: | Line 175: | ||
|S50_FC_DDR_D7 | |S50_FC_DDR_D7 | ||
|[[File:IC-Pin-Out.png|alt=Others|frameless]] | |[[File:IC-Pin-Out.png|alt=Others|frameless]] | ||
| | |Data Input/ Output | ||
|- | |- | ||
|E8 | |E8 | ||
| Line 181: | Line 181: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |DQ Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|E9 | |E9 | ||
| Line 193: | Line 193: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|F2 | |F2 | ||
| Line 199: | Line 199: | ||
| | | | ||
|[[File:Pin-nc.png|alt=Not connected|frameless]] | |[[File:Pin-nc.png|alt=Not connected|frameless]] | ||
| | |No Connect | ||
|- | |- | ||
|F3 | |F3 | ||
| Line 205: | Line 205: | ||
|S50_FC_DDR_ODT0 | |S50_FC_DDR_ODT0 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |On Die Termination | ||
|- | |- | ||
|F7 | |F7 | ||
| Line 211: | Line 211: | ||
|D90_FC_DDR_CLOCK0_P | |D90_FC_DDR_CLOCK0_P | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Clock | ||
|- | |- | ||
|F8 | |F8 | ||
| Line 217: | Line 217: | ||
|D90_FC_DDR_CLOCK0_N | |D90_FC_DDR_CLOCK0_N | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Clock | ||
|- | |- | ||
|F9 | |F9 | ||
| Line 223: | Line 223: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|G1 | |G1 | ||
| Line 235: | Line 235: | ||
| | | | ||
|[[File:Pin-nc.png|alt=Not connected|frameless]] | |[[File:Pin-nc.png|alt=Not connected|frameless]] | ||
| | |No Connect | ||
|- | |- | ||
|G3 | |G3 | ||
| Line 241: | Line 241: | ||
|S50_FC_DDR_CKE0 | |S50_FC_DDR_CKE0 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Clock Enable | ||
|- | |- | ||
|G7 | |G7 | ||
| Line 247: | Line 247: | ||
|S50_FC_DDR_CS0N | |S50_FC_DDR_CS0N | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Chip Select | ||
|- | |- | ||
|G8 | |G8 | ||
| Line 253: | Line 253: | ||
| | | | ||
|[[File:Pin-nc.png|alt=Not connected|frameless]] | |[[File:Pin-nc.png|alt=Not connected|frameless]] | ||
| | |No Connect | ||
|- | |- | ||
|G9 | |G9 | ||
|NC_G9 | |NC_G9 | ||
| | |TEN | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Connectivity Test Mode Enable | ||
|- | |- | ||
|H1 | |H1 | ||
| Line 265: | Line 265: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|H2 | |H2 | ||
| Line 271: | Line 271: | ||
|S50_FC_DDR_WEN | |S50_FC_DDR_WEN | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Command Inputs | ||
|- | |- | ||
|H3 | |H3 | ||
| Line 277: | Line 277: | ||
|S50_FC_DDR_A14 | |S50_FC_DDR_A14 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Activision Command Input | ||
|- | |- | ||
|H7 | |H7 | ||
| Line 283: | Line 283: | ||
|S50_/FC_DDR_CASN | |S50_/FC_DDR_CASN | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Command Inputs | ||
|- | |- | ||
|H8 | |H8 | ||
| Line 289: | Line 289: | ||
|S50_/FC_DDR_RASN | |S50_/FC_DDR_RASN | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Command Inputs | ||
|- | |- | ||
|H9 | |H9 | ||
| Line 301: | Line 301: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Reference voltage for CA | ||
|- | |- | ||
|J2 | |J2 | ||
| Line 307: | Line 307: | ||
|S50_FC_DDR_BA2 | |S50_FC_DDR_BA2 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Bank Group Inputs | ||
|- | |- | ||
|J3 | |J3 | ||
| Line 313: | Line 313: | ||
|S50_FC_DDR_A10 | |S50_FC_DDR_A10 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Auto-precharge | ||
|- | |- | ||
|J7 | |J7 | ||
| Line 319: | Line 319: | ||
|S50_FC_DDR_A12 | |S50_FC_DDR_A12 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Burst Chop | ||
|- | |- | ||
|J8 | |J8 | ||
| Line 325: | Line 325: | ||
|S50_FC_DDR_A15 | |S50_FC_DDR_A15 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Bank Group Inputs | ||
|- | |- | ||
|J9 | |J9 | ||
| Line 331: | Line 331: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|K1 | |K1 | ||
| Line 343: | Line 343: | ||
|S50_FC_DDR_BA0 | |S50_FC_DDR_BA0 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Bank Address Inputs | ||
|- | |- | ||
|K3 | |K3 | ||
| Line 349: | Line 349: | ||
|S50_FC_DDR_A4 | |S50_FC_DDR_A4 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Address Inputs | ||
|- | |- | ||
|K7 | |K7 | ||
| Line 355: | Line 355: | ||
|S50_FC_DDR_A3 | |S50_FC_DDR_A3 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Address Inputs | ||
|- | |- | ||
|K8 | |K8 | ||
| Line 361: | Line 361: | ||
|S50_FC_DDR_BA1 | |S50_FC_DDR_BA1 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Bank Address Inputs | ||
|- | |- | ||
|K9 | |K9 | ||
| Line 373: | Line 373: | ||
|S50_/FC_DDR_RSTN | |S50_/FC_DDR_RSTN | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Active Low Asynchronous Reset | ||
|- | |- | ||
|L2 | |L2 | ||
| Line 379: | Line 379: | ||
|S50_FC_DDR_A6 | |S50_FC_DDR_A6 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Address Inputs | ||
|- | |- | ||
|L3 | |L3 | ||
| Line 385: | Line 385: | ||
|S50_FC_DDR_A0 | |S50_FC_DDR_A0 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Address Inputs | ||
|- | |- | ||
|L7 | |L7 | ||
| Line 391: | Line 391: | ||
|S50_FC_DDR_A1 | |S50_FC_DDR_A1 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Address Inputs | ||
|- | |- | ||
|L8 | |L8 | ||
| Line 397: | Line 397: | ||
|S50_FC_DDR_A5 | |S50_FC_DDR_A5 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Address Inputs | ||
|- | |- | ||
|L9 | |L9 | ||
| Line 403: | Line 403: | ||
|S50_/FC_DDR_ALERTN | |S50_/FC_DDR_ALERTN | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Alert | ||
|- | |- | ||
|M1 | |M1 | ||
| Line 409: | Line 409: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|M2 | |M2 | ||
| Line 415: | Line 415: | ||
|S50_FC_DDR_A8 | |S50_FC_DDR_A8 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Address Inputs | ||
|- | |- | ||
|M3 | |M3 | ||
| Line 421: | Line 421: | ||
|S50_FC_DDR_A2 | |S50_FC_DDR_A2 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Address Inputs | ||
|- | |- | ||
|M7 | |M7 | ||
| Line 427: | Line 427: | ||
|S50_FC_DDR_A9 | |S50_FC_DDR_A9 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Address Inputs | ||
|- | |- | ||
|M8 | |M8 | ||
| Line 433: | Line 433: | ||
|S50_FC_DDR_A7 | |S50_FC_DDR_A7 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Address Inputs | ||
|- | |- | ||
|M9 | |M9 | ||
| Line 439: | Line 439: | ||
|2.5V_DDR4_VPP | |2.5V_DDR4_VPP | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |DRAM Activation Power Supply: 2.5V (2.375V min , 2.75 max) | ||
|- | |- | ||
|N1 | |N1 | ||
| Line 451: | Line 451: | ||
|S50_FC_DDR_A11 | |S50_FC_DDR_A11 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Address Inputs | ||
|- | |- | ||
|N3 | |N3 | ||
| Line 457: | Line 457: | ||
|S50_FC_DDR_PAR | |S50_FC_DDR_PAR | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Command and Address Parity Input | ||
|- | |- | ||
|N7 | |N7 | ||
| Line 463: | Line 463: | ||
| | | | ||
|[[File:Pin-nc.png|alt=Not connected|frameless]] | |[[File:Pin-nc.png|alt=Not connected|frameless]] | ||
| | |No Connect | ||
|- | |- | ||
|N8 | |N8 | ||
| Line 469: | Line 469: | ||
|S50_FC_DDR_A13 | |S50_FC_DDR_A13 | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Address Inputs | ||
|- | |- | ||
|N9 | |N9 | ||
| Line 475: | Line 475: | ||
|1.2V_FC_VDDQMIO | |1.2V_FC_VDDQMIO | ||
|[[File:IC-Pin-in.png|alt=Input|frameless]] | |[[File:IC-Pin-in.png|alt=Input|frameless]] | ||
| | |Power Supply: 1.2 V +/- 0.06 V | ||
|- | |- | ||
|} | |} | ||
Latest revision as of 21:49, 13 December 2024
Pinout[edit | edit source]
| Pad | Internal Name | External Name | Type | Description |
|---|---|---|---|---|
| A1 | VDD_A1 | 1.2V_FC_VDDQMIO | 
|
Power Supply: 1.2 V +/- 0.06 V |
| A2 | VSSQ_A2 | GND |
|
DQ Ground |
| A3 | TDQS_c | 
|
Termination Data Strobe | |
| A7 | DM/DBI/TDQS_t | S50_FC_DDR_DM |
|
Input Data Mask and Data Bus Inversion |
| A8 | VSSQ_A8 | GND |
|
DQ Ground |
| A9 | VSS_A9 | GND |
|
Ground |
| B1 | BPP_B1 | 2.5V_DDR4_VPP |
|
DRAM Activation Power Supply: 2.5V (2.375V min , 2.75 max) |
| B2 | VDDQ_B2 | 1.2V_FC_VDDQMIO |
|
DQ Power Supply: 1.2 V +/- 0.06 V |
| B3 | DQS_c | D90_FC_DDR_DQS0_N | 
|
Data Strobe |
| B7 | DQ1 | S50_FC_DDR_D0 |
|
Data Input/ Output |
| B8 | VDDQ_B8 | 1.2V_FC_VDDQMIO |
|
DQ Power Supply: 1.2 V +/- 0.06 V |
| B9 | ZQ | GND |
|
Reference Pin for ZQ calibration |
| C1 | VDDQ_C1 | 1.2V_FC_VDDQMIO |
|
DQ Power Supply: 1.2 V +/- 0.06 V |
| C2 | DQ0 | S50_FC_DDR_D3 |
|
Data Input/ Output |
| C3 | DQS_t | D90_FC_DDR_DQS0_P |
|
Data Strobe |
| C7 | VDD_C7 | 1.2V_FC_VDDQMIO |
|
Power Supply: 1.2 V +/- 0.06 V |
| C8 | VSS_C8 | GND |
|
Ground |
| C9 | VDDQ_C9 | 1.2V_FC_VDDQMIO |
|
DQ Power Supply: 1.2 V +/- 0.06 V |
| D1 | VSSQ_D1 | GND |
|
DQ Ground |
| D2 | DQ4 | S50_FC_DDR_D4 |
|
Data Input/ Output |
| D3 | DQ2 | S50_FC_DDR_D5 |
|
Data Input/ Output |
| D7 | DQ3 | S50_FC_DDR_D2 |
|
Data Input/ Output |
| D8 | DQ5 | S50_FC_DDR_D1 |
|
Data Input/ Output |
| D9 | VSSQ_D9 | GND |
|
DQ Ground |
| E1 | VSS_E1 | GND |
|
Ground |
| E2 | VDDQ_E2 | 1.2V_FC_VDDQMIO |
|
DQ Power Supply: 1.2 V +/- 0.06 V |
| E3 | DQ6 | S50_FC_DDR_D6 |
|
Data Input/ Output |
| E7 | DQ7 | S50_FC_DDR_D7 |
|
Data Input/ Output |
| E8 | VDDQ_E8 | 1.2V_FC_VDDQMIO |
|
DQ Power Supply: 1.2 V +/- 0.06 V |
| E9 | VSS_E9 | GND |
|
Ground |
| F1 | VDD_F1 | 1.2V_FC_VDDQMIO |
|
Power Supply: 1.2 V +/- 0.06 V |
| F2 | NC_F2 |
|
No Connect | |
| F3 | ODT | S50_FC_DDR_ODT0 |
|
On Die Termination |
| F7 | CK_t | D90_FC_DDR_CLOCK0_P |
|
Clock |
| F8 | CK_c | D90_FC_DDR_CLOCK0_N |
|
Clock |
| F9 | VDD_F9 | 1.2V_FC_VDDQMIO |
|
Power Supply: 1.2 V +/- 0.06 V |
| G1 | VSS_G1 | GND |
|
Ground |
| G2 | NC_G2 |
|
No Connect | |
| G3 | CKE | S50_FC_DDR_CKE0 |
|
Clock Enable |
| G7 | \CS | S50_FC_DDR_CS0N |
|
Chip Select |
| G8 | NC_G8 |
|
No Connect | |
| G9 | NC_G9 | TEN |
|
Connectivity Test Mode Enable |
| H1 | VDD_H1 | 1.2V_FC_VDDQMIO |
|
Power Supply: 1.2 V +/- 0.06 V |
| H2 | \WE/A14 | S50_FC_DDR_WEN |
|
Command Inputs |
| H3 | \ACT | S50_FC_DDR_A14 |
|
Activision Command Input |
| H7 | \CAS | S50_/FC_DDR_CASN |
|
Command Inputs |
| H8 | \RAS | S50_/FC_DDR_RASN |
|
Command Inputs |
| H9 | VSS_G9 | GND |
|
Ground |
| J1 | VREFCA | 1.2V_FC_VDDQMIO |
|
Reference voltage for CA |
| J2 | BG0 | S50_FC_DDR_BA2 |
|
Bank Group Inputs |
| J3 | A10/AP | S50_FC_DDR_A10 |
|
Auto-precharge |
| J7 | A12/\BC | S50_FC_DDR_A12 |
|
Burst Chop |
| J8 | BG1 | S50_FC_DDR_A15 |
|
Bank Group Inputs |
| J9 | VDD_J9 | 1.2V_FC_VDDQMIO |
|
Power Supply: 1.2 V +/- 0.06 V |
| K1 | VSS_K1 | GND |
|
Ground |
| K2 | BA0 | S50_FC_DDR_BA0 |
|
Bank Address Inputs |
| K3 | A4 | S50_FC_DDR_A4 |
|
Address Inputs |
| K7 | A3 | S50_FC_DDR_A3 |
|
Address Inputs |
| K8 | BA1 | S50_FC_DDR_BA1 |
|
Bank Address Inputs |
| K9 | VSS_K9 | GND |
|
Ground |
| L1 | \RESET | S50_/FC_DDR_RSTN |
|
Active Low Asynchronous Reset |
| L2 | A6 | S50_FC_DDR_A6 |
|
Address Inputs |
| L3 | A0 | S50_FC_DDR_A0 |
|
Address Inputs |
| L7 | A1 | S50_FC_DDR_A1 |
|
Address Inputs |
| L8 | A5 | S50_FC_DDR_A5 |
|
Address Inputs |
| L9 | \ALERT | S50_/FC_DDR_ALERTN |
|
Alert |
| M1 | VDD_M1 | 1.2V_FC_VDDQMIO |
|
Power Supply: 1.2 V +/- 0.06 V |
| M2 | A8 | S50_FC_DDR_A8 |
|
Address Inputs |
| M3 | A2 | S50_FC_DDR_A2 |
|
Address Inputs |
| M7 | A9 | S50_FC_DDR_A9 |
|
Address Inputs |
| M8 | A7 | S50_FC_DDR_A7 |
|
Address Inputs |
| M9 | VPP_M9 | 2.5V_DDR4_VPP |
|
DRAM Activation Power Supply: 2.5V (2.375V min , 2.75 max) |
| N1 | VSS_N1 | GND |
|
Ground |
| N2 | A11 | S50_FC_DDR_A11 |
|
Address Inputs |
| N3 | PAR | S50_FC_DDR_PAR |
|
Command and Address Parity Input |
| N7 | NC_N7 |
|
No Connect | |
| N8 | A13 | S50_FC_DDR_A13 |
|
Address Inputs |
| N9 | VDD_N9 | 1.2V_FC_VDDQMIO |
|
Power Supply: 1.2 V +/- 0.06 V |
Pictures[edit | edit source]
