CXD90062GG: Difference between revisions

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(→‎Pinout: Added SSD Controller PCIE)
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== Pinout ==
== Pinout ==
DDR4
'''DDR4'''
{| class="wikitable mw-collapsible"
{| class="wikitable mw-collapsible"
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|+
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|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
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|-
|}
'''PCIE'''
{| class="wikitable mw-collapsible"
|+
!Pad
!Internal Name
!External Name
!Type
!Description
|-
|C24
|PIN_RXN_RC1_0
|D85_M2_PCIE_RX0N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|C25
|PIN_RXP_RC1_0
|D85_M2_PCIE_RX0P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|D21
|PIN_TXN_RC1_0
|D85_M2_PCIE_TX0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|D22
|PIN_TXP_RC1_0
|D85_M2_PCIE_TX0P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|E24
|PIN_RXN_RC1_1
|D85_M2_PCIE_RX1N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|E25
|PIN_RXP_RC1_1
|D85_M2_PCIE_RX1P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|F21
|PIN_TXN_RC1_1
|D85_M2_PCIE_TX1N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|F22
|PIN_TXP_RC1_1
|D85_M2_PCIE_TX1P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|G24
|PIN_RXN_RC1_2
|D85_M2_PCIE_RX2N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|G25
|PIN_RXP_RC1_2
|D85_M2_PCIE_RX2P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|H21
|PIN_TXN_RC1_2
|D85_M2_PCIE_TX2N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|H22
|PIN_TXP_RC1_2
|D85_M2_PCIE_TX2P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|J24
|PIN_RXN_RC1_3
|D85_M2_PCIE_RX3N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|J25
|PIN_RXP_RC1_3
|D85_M2_PCIE_RX3P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|K21
|PIN_TXN_RC1_3
|D85_M2_PCIE_TX3N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|K22
|PIN_TXP_RC1_3
|D85_M2_PCIE_TX3P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|L24
|PIN_RXN_EP_0
|D85_SOC_PCIE_TX3P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|L25
|PIN_RXP_EP_0
|D85_SOC_PCIE_TX3N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|M21
|PIN_TXN_EP_0
|D85_SOC_PCIE_RX3P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|M22
|PIN_TXP_EP_0
|D85_SOC_PCIE_RX3N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|N24
|PIN_RXN_EP_1
|D85_SOC_PCIE_TX2P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|N25
|PIN_RXP_EP_1
|D85_SOC_PCIE_TX2N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|P21
|PIN_TXN_EP_1
|D85_SOC_PCIE_RX2P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|P22
|PIN_TXP_EP_1
|D85_SOC_PCIE_RX2N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|R24
|PIN_RXN_EP_2
|D85_SOC_PCIE_TX1P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|R25
|PIN_RXP_EP_2
|D85_SOC_PCIE_TX1N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|T19
|PIN_PERSTN
|PCIE_PERSTN
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|T21
|PIN_TXN_EP_2
|D85_SOC_PCIE_RX1P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|T22
|PIN_TXP_EP_2
|D85_SOC_PCIE_RX1N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|U24
|PIN_RXN_EP_3
|D85_SOC_PCIE_TX0P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|U25
|PIN_RXP_EP_3
|D85_SOC_PCIE_TX0N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|V21
|PIN_TXN_EP_3
|D85_SOC_PCIE_RX0P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V22
|PIN_TXP_EP_3
|D85_SOC_PCIE_RX0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|W24
|PIN_RXN_RC0
|D85_FC_RX0N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|W25
|PIN_RXP_RC0
|D85_FC_RX0P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|Y21
|PIN_TXN_RC0
|D85_FC_TX0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|Y22
|PIN_TXP_RC0
|D85_FC_TX0P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AA24
|PIN_REFCLK_P_0
|D100G_FC_PCIE_CLK_P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AA25
|PIN_REFCLK_N_0
|D100G_FC_PCIE_CLK_N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AD23
|PIN_CLK_REQ_N_0
|/FC_CLK_REQ_N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|}
|}


Revision as of 18:16, 12 December 2024

NVME Controller


Pinout

DDR4

Pad Internal Name External Name Type Description
AA12 PIN_VREFSMIO 1.2V_FC_VDDQMIO Input
AB7 PIN_M_A[15] S50_FC_DDR_A15 Output
AB8 PIN_M_A[11] S50_FC_DDR_A11 Output
AB9 PIN_M_A[8] S50_FC_DDR_A8 Output
AB10 PIN_M_A[4] S50_FC_DDR_A4 Output
AB11 PIN_M_ALERT_N S50_/FC_DDR_ALERTN Output
AB12 PIN_DDR_CAL GND Input Ground
AB13 PIN_M_ODT[0] S50_FC_DDR_ODT0 Output
AB14 PIN_M_CS_N[0] S50_FC_DDR_CS0N Output
AB15 PIN_M_D[7] S50_FC_DDR_D7 Others
AB16 PIN_M_D[6] S50_FC_DDR_D6 Others
AB17 PIN_M_D[2] S50_FC_DDR_D2 Others
AB18 PIN_M_D[1] S50_FC_DDR_D1 Others
AB19 PIN_M_DM S50_FC_DDR_DM Output
AC7 PIN_M_A[14] S50_FC_DDR_A14 Output
AC9 PIN_M_A[7] S50_FC_DDR_A7 Output
AC10 PIN_M_A[3] S50_FC_DDR_A3 Output
AC12 PIN_M_PAR S50_FC_DDR_PAR Output
AC14 PIN_M_CS_N[1] N/C Not connected No Connection
AC15 PIN_M_WE_N S50_FC_DDR_WEN Output
AC17 PIN_M_D[3] S50_FC_DDR_D3 Others
AC19 PIN_M_D[0] S50_FC_DDR_D0 Others
AD7 PIN_M_A[13] S50_FC_DDR_A13 Output
AD8 PIN_M_A[9] S50_FC_DDR_A9 Output
AD9 PIN_M_A[6] S50_FC_DDR_A6 Output
AD10 PIN_M_A[2] S50_FC_DDR_A2 Output
AD11 PIN_M_BA[2] S50_FC_DDR_BA2 Output
AD12 PIN_M_BA[0] S50_FC_DDR_BA0 Output
AD13 PIN_M_ODT[1] N/C Not connected No Connection
AD14 PIN_M_CKE[0] S50_FC_DDR_CKE0 Output
AD15 PIN_M_CAS_N S50_/FC_DDR_CASN Output
AD16 PIN_M_CLOCK[0] D90_FC_DDR_CLOCK0_P Output
AD17 PIN_M_D[4] S50_FC_DDR_D4 Others
AD18 PIN_M_DQS_P[0] D90_FC_DDR_DQS0_P Others
AE7 PIN_M_A[12] S50_FC_DDR_A12 Output
AE8 PIN_M_A[10] S50_FC_DDR_A10 Output
AE9 PIN_M_A[5] S50_FC_DDR_A5 Output
AE10 PIN_M_A[1] S50_FC_DDR_A1 Output
AE11 PIN_M_A[0] S50_FC_DDR_A0 Output
AE12 PIN_M_BA[1] S50_FC_DDR_BA1 Output
AE13 PIN_M_RST_N NS50_/FC_DDR_RSTN Output
AE14 PIN_M_CKE[1] GND Input Ground
AE15 PIN_M_RAS_N S50_/FC_DDR_RASN Output
AE16 PIN_M_CLOCK_N[0] D90_FC_DDR_CLOCK0_N Output
AE17 PIN_M_D[5] S50_FC_DDR_D5 Others
AE18 PIN_M_DQS_N[0] D90_FC_DDR_DQS0_N Others

PCIE

Pad Internal Name External Name Type Description
C24 PIN_RXN_RC1_0 D85_M2_PCIE_RX0N Input
C25 PIN_RXP_RC1_0 D85_M2_PCIE_RX0P Input
D21 PIN_TXN_RC1_0 D85_M2_PCIE_TX0N Output
D22 PIN_TXP_RC1_0 D85_M2_PCIE_TX0P Output
E24 PIN_RXN_RC1_1 D85_M2_PCIE_RX1N Input
E25 PIN_RXP_RC1_1 D85_M2_PCIE_RX1P Input
F21 PIN_TXN_RC1_1 D85_M2_PCIE_TX1N Output
F22 PIN_TXP_RC1_1 D85_M2_PCIE_TX1P Output
G24 PIN_RXN_RC1_2 D85_M2_PCIE_RX2N Input
G25 PIN_RXP_RC1_2 D85_M2_PCIE_RX2P Input
H21 PIN_TXN_RC1_2 D85_M2_PCIE_TX2N Output
H22 PIN_TXP_RC1_2 D85_M2_PCIE_TX2P Output
J24 PIN_RXN_RC1_3 D85_M2_PCIE_RX3N Input
J25 PIN_RXP_RC1_3 D85_M2_PCIE_RX3P Input
K21 PIN_TXN_RC1_3 D85_M2_PCIE_TX3N Output
K22 PIN_TXP_RC1_3 D85_M2_PCIE_TX3P Output
L24 PIN_RXN_EP_0 D85_SOC_PCIE_TX3P Input
L25 PIN_RXP_EP_0 D85_SOC_PCIE_TX3N Input
M21 PIN_TXN_EP_0 D85_SOC_PCIE_RX3P Output
M22 PIN_TXP_EP_0 D85_SOC_PCIE_RX3N Output
N24 PIN_RXN_EP_1 D85_SOC_PCIE_TX2P Input
N25 PIN_RXP_EP_1 D85_SOC_PCIE_TX2N Input
P21 PIN_TXN_EP_1 D85_SOC_PCIE_RX2P Output
P22 PIN_TXP_EP_1 D85_SOC_PCIE_RX2N Output
R24 PIN_RXN_EP_2 D85_SOC_PCIE_TX1P Input
R25 PIN_RXP_EP_2 D85_SOC_PCIE_TX1N Input
T19 PIN_PERSTN PCIE_PERSTN Output
T21 PIN_TXN_EP_2 D85_SOC_PCIE_RX1P Output
T22 PIN_TXP_EP_2 D85_SOC_PCIE_RX1N Output
U24 PIN_RXN_EP_3 D85_SOC_PCIE_TX0P Input
U25 PIN_RXP_EP_3 D85_SOC_PCIE_TX0N Input
V21 PIN_TXN_EP_3 D85_SOC_PCIE_RX0P Output
V22 PIN_TXP_EP_3 D85_SOC_PCIE_RX0N Output
W24 PIN_RXN_RC0 D85_FC_RX0N Input
W25 PIN_RXP_RC0 D85_FC_RX0P Input
Y21 PIN_TXN_RC0 D85_FC_TX0N Output
Y22 PIN_TXP_RC0 D85_FC_TX0P Output
AA24 PIN_REFCLK_P_0 D100G_FC_PCIE_CLK_P Input
AA25 PIN_REFCLK_N_0 D100G_FC_PCIE_CLK_N Input
AD23 PIN_CLK_REQ_N_0 /FC_CLK_REQ_N Output

Pictures

CXD90062GG.jpeg
CXD90062GG2.jpeg
50980106477 3117f2d5c0 o.jpg CXD90062GG Proto.png

Sources

https://www.flickr.com/photos/130561288@N04/albums/72157718290760702

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