CP Box Non Volatile Storage: Difference between revisions
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| Line 34: | Line 34: | ||
|0x01 | |0x01 | ||
|DDR capacity: | |DDR capacity: | ||
'''01''' = 256 MiB | |||
'''02''' = 512 MiB | * '''01''' = 256 MiB | ||
'''03''' = 1 GiB | * '''02''' = 512 MiB | ||
'''04''' = 2 GiB | * '''03''' = 1 GiB | ||
'''05''' = 4 GiB | * '''04''' = 2 GiB | ||
'''06''' = 8 GiB | * '''05''' = 4 GiB | ||
'''07''' = 16 GiB | * '''06''' = 8 GiB | ||
'''FF''' = 4 GiB | * '''07''' = 16 GiB | ||
* '''FF''' = 4 GiB | |||
|05 | |05 | ||
| | | | ||
| Line 77: | Line 78: | ||
|0x01 | |0x01 | ||
|DDR memory controller initialization mode: | |DDR memory controller initialization mode: | ||
'''00''' = Skip initialization at all | |||
'''01''' = Initialize DDR3 MC | * '''00''' = Skip initialization at all | ||
'''02''' = Initialize DDR4 MC | * '''01''' = Initialize DDR3 MC | ||
* '''02''' = Initialize DDR4 MC | |||
|00 | |00 | ||
| | | | ||
| Line 130: | Line 132: | ||
|Flag to toggle EMC checksum validation for | |Flag to toggle EMC checksum validation for | ||
several NVS blocks (ID, HWCTRL, THERMAL): | several NVS blocks (ID, HWCTRL, THERMAL): | ||
'''FF''' = Disabled | |||
'''otherwise''' = Enabled | * '''FF''' = Disabled | ||
* '''otherwise''' = Enabled | |||
|FF | |FF | ||
|Disabled by default | |Disabled by default | ||
| Line 143: | Line 146: | ||
|- | |- | ||
| 0x1012 || 0x1C5012 || 0x01 || Flag to toggle EMC UART: | | 0x1012 || 0x1C5012 || 0x01 || Flag to toggle EMC UART: | ||
'''FF''' = Enabled | |||
'''otherwise''' = Disabled | * '''FF''' = Enabled | ||
* '''otherwise''' = Disabled | |||
|FF | |FF | ||
|Enabled by default | |Enabled by default | ||
| Line 166: | Line 170: | ||
|0x01 | |0x01 | ||
|Flag to toggle mode: | |Flag to toggle mode: | ||
'''FF''' = Normal | |||
'''otherwise''' = Special (private?) | * '''FF''' = Normal | ||
* '''otherwise''' = Special (private?) | |||
|FF | |FF | ||
|Normal mode is set by default | |Normal mode is set by default | ||
Revision as of 14:55, 1 September 2023
CP Box contains its own NVS (Non-Volatile Storage) which is loaded from main serial flash (Winbond 25Q256JVEQ) and consists of multiple partitions.
NVS structure
| Offset @ NVS | Offset @ Flash | Size | Description | Sample Data | Notes |
|---|---|---|---|---|---|
| 0x0000 | 0x1C4000 | 0x08 | Board ID (e.g. 0x2001010101010501) | 20 01 01 01 01 01 04 01 | Can be seen at EAP boot log |
| 0x0021 | 0x1C4021 | 0x06 | MAC address of CP Box (78:C8:81:62:A9:D6) | 78 C8 81 62 A9 D6 | 78 C8 81 XX XX XX |
| 0x0027 | 0x1C4027 | 0x06 | 2nd MAC address | FF FF FF FF FF FF | Used in special conditions? |
| 0x0060 | 0x1C4060 | 0x01 | DDR capacity:
|
05 | |
| 0x0061 | 0x1C4061 | 0x01 | DDR number of device | 02 | |
| 0x0062 | 0x1C4062 | 0x01 | DDR number of rank | 01 | |
| 0x0063 | 0x1C4063 | 0x01 | DDR device width | 01 | |
| 0x0064 | 0x1C4064 | 0x01 | DDR bus width | 02 | |
| 0x0065 | 0x1C4065 | 0x01 | DDR memory controller initialization mode:
|
00 | |
| 0x00A0 | 0x1C40A0 | 0x01 | Related to L2? | ||
| 0x0071 | 0x1C4071 | 0x01 | Related to error notifications? | ||
| 0x0077 | 0x1C4077 | 0x01 | Related to power sequence? | ||
| 0x007A | 0x1C407A | 0x01 | |||
| 0x0203 | 0x1C4203 | 0x01 | Related to error notifications? | ||
| 0x0211 | 0x1C4211 | 0x01 | GbE trace length | FF | |
| 0x1010 | 0x1C5010 | 0x01 | Flag to toggle EMC checksum validation for
several NVS blocks (ID, HWCTRL, THERMAL):
|
FF | Disabled by default |
| 0x1011 | 0x1C5011 | 0x01 | |||
| 0x1012 | 0x1C5012 | 0x01 | Flag to toggle EMC UART:
|
FF | Enabled by default |
| 0x1014 | 0x1C5014 | 0x01 | FF | ||
| 0x1015 | 0x1C5015 | 0x01 | FF | ||
| 0x1022 | 0x1C5022 | 0x01 | Flag to toggle mode:
|
FF | Normal mode is set by default |
| 0x1200 | 0x1C5200 | 0x0400 | Error log | FFs | Empty by default |
| 0x4000 | 0x1C8000 | 0x10 | Serial Number (e.g. 1AR2P20000001100) | 31 41 52 32 50 32 30 30 30 30 30 30 31 31 30 30 |