CXD90062GG: Difference between revisions

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(→‎Pinout: change pins order)
 
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NVME Controller  
* NVME Controller, Codename Titania
 
 
 
== Pinout ==
{| class="wikitable mw-collapsible"
|+
!Pad
!Internal Name
!External Name
!Type
!Description
|-
|A1
|VSS_A1
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|A2
|VSS_A2
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|A3
|PIN_REB_CH6
|D90_NAND_CH6_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|A4
|PIN_CLE_CH6
|S50_NAND_CH6_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|A5
|PIN_AD_CH7[1]
|S50_NAND_CH7_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|A6
|PIN_DQSB_CH7
|D90_NAND_CH7_DQS_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|A7
|PIN_AD_CH7[7]
|S50_NAND_CH7_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|A8
|PIN_REB_CH7
|D90_NAND_CH7_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|A9
|PIN_AD_CH8[1]
|S50_NAND_CH8_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|A10
|PIN_DQS_CH8
|D90_NAND_CH8_DQS_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|A11
|PIN_AD_CH8[7]
|S50_NAND_CH8_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|A12
|PIN_REB_CH8
|D90_NAND_CH8_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|A13
|PIN_DQS_CH9
|D90_NAND_CH9_DQS_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|A14
|PIN_AD_CH9[7]
|S50_NAND_CH9_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|A15
|PIN_REB_CH9
|D90_NAND_CH9_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|A16
|PIN_DQSB_CH10
|D90_NAND_CH10_DQS_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|A17
|PIN_AD_CH10[4]
|S50_NAND_CH10_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|A18
|PIN_REB_CH10
|D90_NAND_CH10_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|A19
|PIN_AD_CH11[0]
|S50_NAND_CH11_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|A20
|PIN_DQSB_CH11
|D90_NAND_CH11_DQS_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|A21
|PIN_AD_CH11[6]
|S50_NAND_CH11_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|A22
|PIN_RE_CH11
|D90_NAND_CH11_RE_ P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|A23
|PIN_CLE_CH11
|S50_NAND_CH11_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|A24
|VSS_A24
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|A25
|VSS_A25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|B1
|VSS_B1
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|B2
|PIN_AD_CH6[6]
|S50_NAND_CH6_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B3
|PIN_RE_CH6
|D90_NAND_CH6_RE_ P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|B4
|PIN_ALE_CH6
|S50_NAND_CH6_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|B5
|PIN_AD_CH7[0]
|S50_NAND_CH7_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B6
|PIN_DQS_CH7
|D90_NAND_CH7_DQS_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B7
|PIN_AD_CH7[6]
|S50_NAND_CH7_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B8
|PIN_RE_CH7
|D90_NAND_CH7_RE_ P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|B9
|PIN_AD_CH8[0]
|S50_NAND_CH8_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B10
|PIN_DQSB_CH8
|D90_NAND_CH8_DQS_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B11
|PIN_AD_CH8[6]
|S50_NAND_CH8_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B12
|PIN_RE_CH8
|D90_NAND_CH8_RE_ P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|B13
|PIN_DQSB_CH9
|D90_NAND_CH9_DQS_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B14
|PIN_AD_CH9[6]
|S50_NAND_CH9_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B15
|PIN_RE_CH9
|D90_NAND_CH9_RE_ P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|B16
|PIN_DQS_CH10
|D90_NAND_CH10_DQS_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B17
|PIN_AD_CH10[5]
|S50_NAND_CH10_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B18
|PIN_RE_CH10
|D90_NAND_CH10_RE_ P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|B19
|PIN_AD_CH11[1]
|S50_NAND_CH11_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B20
|PIN_DQS_CH11
|D90_NAND_CH11_DQS_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B21
|PIN_AD_CH11[7]
|S50_NAND_CH11_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|B22
|PIN_REB_CH11
|D90_NAND_CH11_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|B23
|VSS_B23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|B24
|VSS_B24
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|B25
|VSS_B25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|C1
|PIN_DQSB_CH6
|D90_NAND_CH6_DQS_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|C2
|PIN_DQS_CH6
|D90_NAND_CH6_DQS_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|C3
|VSS_C3
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|C4
|PIN_AD_CH6[7]
|S50_NAND_CH6_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|C5
|PIN_CE0_CH6
|S50_/NAND_CH6_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|C6
|VSS_C6
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|C7
|PIN_AD_CH7[5]
|S50_NAND_CH7_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|C8
|VSS_C8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|C9
|PIN_CE1_CH7
|S50_/NAND_CH7_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|C10
|PIN_AD_CH8[4]
|S50_NAND_CH8_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|C11
|VSS_C11
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|C12
|PIN_CE1_CH8
|S50_/NAND_CH8_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|C13
|PIN_AD_CH9[3]
|S50_NAND_CH9_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|C14
|VSS_C14
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|C15
|PIN_CLE_CH9
|S50_NAND_CH9_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|C16
|PIN_AD_CH10[0]
|S50_NAND_CH10_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|C17
|VSS_C17
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|C18
|PIN_CLE_CH10
|S50_NAND_CH10_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|C19
|PIN_AD_CH11[2]
|S50_NAND_CH11_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|C20
|PIN_WE_CH11
|NAND_CH11_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|C21
|VSS_C21
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|C22
|VSS_C22
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|C23
|VSS_C23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|C24
|PIN_RXN_RC1_0
|D85_M2_PCIE_RX0N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|C25
|PIN_RXP_RC1_0
|D85_M2_PCIE_RX0P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|D1
|PIN_AD_CH6[3]
|S50_NAND_CH6_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|D2
|PIN_AD_CH6[2]
|S50_NAND_CH6_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|D3
|PIN_AD_CH6[5]
|S50_NAND_CH6_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|D4
|PIN_AD_CH6[4]
|S50_NAND_CH6_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|D5
|PIN_WE_CH6
|NAND_CH6_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|D6
|PIN_AD_CH7[2]
|S50_NAND_CH7_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|D7
|PIN_AD_CH7[4]
|S50_NAND_CH7_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|D8
|PIN_CLE_CH7
|S50_NAND_CH7_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|D9
|PIN_CE0_CH7
|S50_/NAND_CH7_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|D10
|PIN_AD_CH8[3]
|S50_NAND_CH8_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|D11
|PIN_AD_CH8[5]
|S50_NAND_CH8_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|D12
|PIN_CE0_CH8
|S50_/NAND_CH8_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|D13
|PIN_AD_CH9[2]
|S50_NAND_CH9_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|D14
|PIN_AD_CH9[5]
|S50_NAND_CH9_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|D15
|PIN_ALE_CH9
|S50_NAND_CH9_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|D16
|PIN_AD_CH10[1]
|S50_NAND_CH10_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|D17
|PIN_AD_CH10[6]
|S50_NAND_CH10_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|D18
|PIN_ALE_CH10
|S50_NAND_CH10_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|D19
|PIN_AD_CH11[3]
|S50_NAND_CH11_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|D20
|VSS_D20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|D21
|PIN_TXN_RC1_0
|D85_M2_PCIE_TX0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|D22
|PIN_TXP_RC1_0
|D85_M2_PCIE_TX0P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|D23
|VSS_D23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|D24
|VSS_D24
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|D25
|VSS_D25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|E1
|PIN_RE_CH5
|D90_NAND_CH5_RE_ P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|E2
|PIN_REB_CH5
|D90_NAND_CH5_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|E3
|VSS_E3
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|E4
|PIN_AD_CH6[1]
|S50_NAND_CH6_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|E5
|PIN_AD_CH6[0]
|S50_NAND_CH6_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|E6
|PIN_CE1_CH6
|S50_/NAND_CH6_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|E7
|PIN_AD_CH7[3]
|S50_NAND_CH7_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|E8
|PIN_WE_CH7
|NAND_CH7_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|E9
|PIN_ALE_CH7
|S50_NAND_CH9_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|E10
|PIN_AD_CH8[2]
|S50_NAND_CH8_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|E11
|PIN_WE_CH8
|NAND_CH8_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|E12
|PIN_ALE_CH8
|S50_NAND_CH8_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|E13
|PIN_AD_CH9[1]
|S50_NAND_CH9_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|E14
|PIN_AD_CH9[4]
|S50_NAND_CH9_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|E15
|PIN_CE0_CH9
|S50_/NAND_CH9_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|E16
|PIN_AD_CH10[2]
|S50_NAND_CH10_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|E17
|PIN_AD_CH10[7]
|S50_NAND_CH10_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|E18
|PIN_CE0_CH10
|S50_/NAND_CH10_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|E19
|PIN_AD_CH11[5]
|S50_NAND_CH11_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|E20
|PIN_ALE_CH11
|S50_NAND_CH11_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|E21
|VSS_E21
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|E22
|VSS_E22
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|E23
|VSS_E23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|E24
|PIN_RXN_RC1_1
|D85_M2_PCIE_RX1N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|E25
|PIN_RXP_RC1_1
|D85_M2_PCIE_RX1P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|F1
|PIN_AD_CH5[4]
|S50_NAND_CH5_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|F2
|PIN_AD_CH5[5]
|S50_NAND_CH5_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|F3
|PIN_CLE_CH5
|S50_NAND_CH5_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|F4
|PIN_ALE_CH5
|S50_NAND_CH5_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|F5
|PIN_CE0_CH5
|S50_/NAND_CH5_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|F6
|PIN_CE2_CH6
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|F7
|PIN_CE3_CH6
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|F8
|PIN_CE3_CH7
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|F9
|PIN_CE2_CH7
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|F10
|VSS_F10
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|F11
|PIN_CE2_CH8
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|F12
|PIN_CLE_CH8
|S50_NAND_CH8_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|F13
|PIN_AD_CH9[0]
|S50_NAND_CH9_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|F14
|PIN_WE_CH9
|NAND_CH9_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|F15
|PIN_CE1_CH9
|S50_/NAND_CH9_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|F16
|PIN_AD_CH10[3]
|S50_NAND_CH10_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|F17
|PIN_WE_CH10
|NAND_CH10_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|F18
|PIN_CE1_CH10
|S50_/NAND_CH10_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|F19
|PIN_AD_CH11[4]
|S50_NAND_CH11_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|F20
|VSS_F20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|F21
|PIN_TXN_RC1_1
|D85_M2_PCIE_TX1N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|F22
|PIN_TXP_RC1_1
|D85_M2_PCIE_TX1P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|F23
|VSS_F23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|F24
|VSS_F24
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|F25
|VSS_F25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|G1
|PIN_DQS_CH5
|D90_NAND_CH5_DQS_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|G2
|PIN_DQSB_CH5
|D90_NAND_CH5_DQS_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|G3
|PIN_AD_CH5[6]
|S50_NAND_CH5_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|G4
|PIN_AD_CH5[7]
|S50_NAND_CH5_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|G5
|PIN_WE_CH5
|NAND_CH5_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|G6
|PIN_CE1_CH5
|S50_/NAND_CH5_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|G7
|VSS_G7
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|G8
|VSS_G8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|G9
|VSS_G9
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|G10
|VSS_G10
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|G11
|PIN_CE3_CH8
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|G12
|VSS_G12
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|G13
|VSS_G13
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|G14
|PIN_CE3_CH9
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|G15
|PIN_CE2_CH9
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|G16
|VSS_G16
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|G17
|PIN_CE2_CH10
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|G18
|PIN_CE3_CH10
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|G19
|PIN_CE0_CH11
|S50_/NAND_CH11_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|G20
|PIN_CE1_CH11
|S50_/NAND_CH11_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|G21
|VSS_G21
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|G22
|VSS_G22
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|G23
|VSS_G23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|G24
|PIN_RXN_RC1_2
|D85_M2_PCIE_RX2N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|G25
|PIN_RXP_RC1_2
|D85_M2_PCIE_RX2P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|H1
|PIN_AD_CH5[0]
|S50_NAND_CH5_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|H2
|PIN_AD_CH5[1]
|S50_NAND_CH5_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|H3
|VSS_H3
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|H4
|PIN_AD_CH5[2]
|S50_NAND_CH5_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|H5
|PIN_AD_CH5[3]
|S50_NAND_CH5_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|H6
|PIN_CE2_CH5
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|H7
|PIN_CE3_CH5
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|H8
|VSS_H8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|H9
|VSS_H9
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|H10
|VSS_H10
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|H11
|VSS_H11
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|H12
|VSS_H12
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|H13
|PIN_VREF_NF[1]
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|H14
|VSS_H14
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|H15
|VSS_H15
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|H16
|VSS_H16
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|H17
|VSS_H17
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|H18
|PIN_CE3_CH11
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|H19
|PIN_CE2_CH11
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|H20
|VSS_H20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|H21
|PIN_TXN_RC1_2
|D85_M2_PCIE_TX2N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|H22
|PIN_TXP_RC1_2
|D85_M2_PCIE_TX2P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|H23
|VSS_H23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|H24
|VSS_H24
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|H25
|VSS_H25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|J1
|PIN_REB_CH4
|D90_NAND_CH4_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|J2
|PIN_RE_CH4
|D90_NAND_CH4_RE_ P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|J3
|PIN_CLE_CH4
|S50_NAND_CH4_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|J4
|PIN_ALE_CH4
|S50_NAND_CH4_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|J5
|PIN_CE0_CH4
|S50_/NAND_CH4_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|J6
|PIN_CE1_CH4
|S50_/NAND_CH4_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|J7
|PIN_CE3_CH4
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|J8
|VSS_J8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|J9
|VSS_J9
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|J10
|VDDOFIO_J10
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|J11
|VDDOFIO_J11
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|J12
|VDDOFIO_J12
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|J13
|VSS_J13
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|J14
|VDDOFIO_J14
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|J15
|VDDOFIO_J15
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|J16
|VDDOFIO_J16
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|J17
|VSS_J17
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|J18
|VSS_J18
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|J19
|VSS_J19
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|J20
|VSS_J20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|J21
|VSS_J21
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|J22
|VSS_J22
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|J23
|VSS_J23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|J24
|PIN_RXN_RC1_3
|D85_M2_PCIE_RX3N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|J25
|PIN_RXP_RC1_3
|D85_M2_PCIE_RX3P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|K1
|PIN_AD_CH4[4]
|S50_NAND_CH4_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|K2
|PIN_AD_CH4[5]
|S50_NAND_CH4_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|K3
|VSS_K3
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|K4
|PIN_AD_CH4[6]
|S50_NAND_CH4_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|K5
|PIN_AD_CH4[7]
|S50_NAND_CH4_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|K6
|PIN_WE_CH4
|NAND_CH4_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|K7
|PIN_CE2_CH4
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|K8
|VSS_K8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|K9
|VSS_K9
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|K10
|VDD_K10
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|K11
|VDD_K11
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|K12
|VSS_K12
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|K13
|VSS_K13
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|K14
|VDD_K14
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|K15
|VDD_K15
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|K16
|VSS_K16
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|K17
|VSS_K17
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|K18
|VSS_K18
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|K19
|VSS_K19
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|K20
|VSS_K20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|K21
|PIN_TXN_RC1_3
|D85_M2_PCIE_TX3N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|K22
|PIN_TXP_RC1_3
|D85_M2_PCIE_TX3P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|K23
|VSS_K23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|K24
|VSS_K24
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|K25
|VSS_K25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|L1
|PIN_DQS_CH4
|D90_NAND_CH4_DQS_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|L2
|PIN_DQSB_CH4
|D90_NAND_CH4_DQS_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|L3
|PIN_AD_CH4[3]
|S50_NAND_CH4_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|L4
|PIN_AD_CH4[2]
|S50_NAND_CH4_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|L5
|PIN_AD_CH4[1]
|S50_NAND_CH4_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|L6
|PIN_AD_CH4[0]
|S50_NAND_CH4_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|L7
|VSS_L7
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|L8
|VSS_L8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|L9
|VDDOFIO_L9
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|L10
|VSS_L10
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|L11
|VSS_L11
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|L12
|VDD_L12
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|L13
|VDD_L13
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|L14
|VSS_L14
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|L15
|VSS_L15
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|L16
|VDD_L16
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|L17
|AVDD18_PCIE_L17
|1.8V_FC_AVDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|L18
|VSS_L18
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|L19
|VSS_L19
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|L20
|VSS_L20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|L21
|VSS_L21
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|L22
|VSS_L22
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|L23
|VSS_L23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|L24
|PIN_RXN_EP_0
|D85_SOC_PCIE_TX3P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|L25
|PIN_RXP_EP_0
|D85_SOC_PCIE_TX3N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|M1
|PIN_REB_CH3
|D90_NAND_CH3_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|M2
|PIN_RE_CH3
|D90_NAND_CH3_RE_ P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|M3
|PIN_CE1_CH3
|S50_/NAND_CH3_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|M4
|PIN_CE0_CH3
|S50_/NAND_CH3_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|M5
|PIN_ALE_CH3
|S50_NAND_CH3_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|M6
|PIN_CLE_CH3
|S50_NAND_CH3_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|M7
|PIN_CE2_CH3
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|M8
|PIN_CAL_NF
|S50_/NAND_WP
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|M9
|VDDOFIO_M9
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|M10
|VDD_M10
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|M11
|VDD_M11
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|M12
|VSS_M12
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|M13
|VSS_M13
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|M14
|VDD_M14
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|M15
|VDD_M15
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|M16
|VSS_M16
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|M17
|AVDD18_PCIE_M17
|1.8V_FC_AVDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|M18
|VSS_M18
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|M19
|VSS_M19
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|M20
|VSS_M20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|M21
|PIN_TXN_EP_0
|D85_SOC_PCIE_RX3P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|M22
|PIN_TXP_EP_0
|D85_SOC_PCIE_RX3N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|M23
|VSS_M23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|M24
|VSS_M24
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|M25
|VSS_M25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N1
|PIN_AD_CH3[7]
|S50_NAND_CH3_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|N2
|PIN_AD_CH3[6]
|S50_NAND_CH3_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|N3
|VSS_N3
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N4
|PIN_AD_CH3[5]
|S50_NAND_CH3_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|N5
|PIN_AD_CH3[4]
|S50_NAND_CH3_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|N6
|PIN_WE_CH3
|NAND_CH3_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|N7
|PIN_CE3_CH3
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|N8
|PIN_VREF_NF[0]
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|N9
|VSS_N9
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N10
|VSS_N10
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N11
|VSS_N11
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N12
|VDD_N12
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|N13
|VDD_N13
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|N14
|VSS_N14
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N15
|VSS_N15
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N16
|VDD_N16
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|N17
|VSS_N17
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N18
|VSS_N18
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N19
|VSS_N19
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N20
|VSS_N20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N21
|VSS_N21
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N22
|VSS_N22
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N23
|VSS_N23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|N24
|PIN_RXN_EP_1
|D85_SOC_PCIE_TX2P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|N25
|PIN_RXP_EP_1
|D85_SOC_PCIE_TX2N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|P1
|PIN_DQSB_CH3
|D90_NAND_CH3_DQS_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|P2
|PIN_DQS_CH3
|D90_NAND_CH3_DQS_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|P3
|PIN_AD_CH3[3]
|S50_NAND_CH3_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|P4
|PIN_AD_CH3[2]
|S50_NAND_CH3_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|P5
|PIN_AD_CH3[1]
|S50_NAND_CH3_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|P6
|PIN_AD_CH3[0]
|S50_NAND_CH3_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|P7
|VSS_P7
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|P8
|VSS_P8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|P9
|VDDOFIO_P9
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|P10
|VDD_P10
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|P11
|VDD_P11
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|P12
|VSS_P12
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|P13
|VSS_P13
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|P14
|VDD_P14
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|P15
|VDD_P15
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|P16
|VSS_P16
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|P17
|AVDD18_PCIE_P17
|1.8V_FC_AVDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|P18
|VSS_P18
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|P19
|VSS_P19
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|P20
|VSS_P20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|P21
|PIN_TXN_EP_1
|D85_SOC_PCIE_RX2P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|P22
|PIN_TXP_EP_1
|D85_SOC_PCIE_RX2N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|P23
|VSS_P23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|P24
|VSS_P24
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|P25
|VSS_P25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|R1
|PIN_REB_CH2
|D90_NAND_CH2_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|R2
|PIN_RE_CH2
|D90_NAND_CH2_RE_ P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|R3
|PIN_CE1_CH2
|S50_/NAND_CH2_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|R4
|PIN_CE0_CH2
|S50_/NAND_CH2_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|R5
|PIN_ALE_CH2
|S50_NAND_CH2_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|R6
|PIN_CLE_CH2
|S50_NAND_CH2_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|R7
|PIN_CE2_CH2
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|R8
|VSS_R8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|R9
|VDDOFIO_R9
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|R10
|VSS_R10
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|R11
|VSS_R11
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|R12
|VDD_R12
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|R13
|VDD_R13
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|R14
|VSS_R14
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|R15
|VSS_R15
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|R16
|VDD_R16
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|R17
|AVDD18_PCIE_R17
|1.8V_FC_AVDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|R18
|VSS_R18
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|R19
|VSS_R19
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|R20
|VSS_R20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|R21
|VSS_R21
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|R22
|VSS_R22
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|R23
|VSS_R23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|R24
|PIN_RXN_EP_2
|D85_SOC_PCIE_TX1P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|R25
|PIN_RXP_EP_2
|D85_SOC_PCIE_TX1N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|T1
|PIN_AD_CH2[7]
|S50_NAND_CH2_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|T2
|PIN_AD_CH2[6]
|S50_NAND_CH2_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|T3
|VSS_T3
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|T4
|PIN_AD_CH2[5]
|S50_NAND_CH2_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|T5
|PIN_AD_CH2[4]
|S50_NAND_CH2_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|T6
|PIN_WE_CH2
|NAND_CH2_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|T7
|PIN_CE3_CH2
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|T8
|VSS_T8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|T9
|VDDOFIO_T9
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|T10
|VDD_T10
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|T11
|VDD_T11
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|T12
|VSS_T12
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|T13
|VDDO_MISC
|3.3V_FC_VDDQ_MISC
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|T14
|VDD_T14
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|T15
|VDD_T15
|0.8V_FC_VDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|T16
|VSS_T16
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|T17
|PIN_ISET
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|T18
|VSS_T18
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|T19
|PIN_PERSTN
|PCIE_PERSTN
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|T20
|VSS_T20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|T21
|PIN_TXN_EP_2
|D85_SOC_PCIE_RX1P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|T22
|PIN_TXP_EP_2
|D85_SOC_PCIE_RX1N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|T23
|VSS_T23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|T24
|VSS_T24
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|T25
|VSS_T25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|U1
|PIN_DQSB_CH2
|D90_NAND_CH2_DQS_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|U2
|PIN_DQS_CH2
|D90_NAND_CH2_DQS_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|U3
|PIN_AD_CH2[3]
|S50_NAND_CH2_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|U4
|PIN_AD_CH2[2]
|S50_NAND_CH2_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|U5
|PIN_AD_CH2[1]
|S50_NAND_CH2_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|U6
|PIN_AD_CH2[0]
|S50_NAND_CH2_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|U7
|VSS_U7
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|U8
|VSS_U8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|U9
|VSS_U9
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|U10
|VDDQMIO_U10
|1.2V_FC_VDDQMIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|U11
|VDDQMIO_U11
|1.2V_FC_VDDQMIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|U12
|VDDQMIO_U12
|1.2V_FC_VDDQMIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|U13
|AVDD18_PLLA
|1.8V_FC_AVDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|U14
|VSS_U14
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|U15
|VDDO_MISC_1P8V
|1.8V_FC_AVDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|U16
|AVDD18_EFUSE
|1.8V_FC_AVDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|U17
|VSS_U17
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|U18
|AVDD18_ANA
|1.8V_FC_AVDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|U19
|PIN_JT0_CLK
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|U20
|VSS_U20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|U21
|VSS_U21
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|U22
|VSS_U22
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|U23
|VSS_U23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|U24
|PIN_RXN_EP_3
|D85_SOC_PCIE_TX0P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|U25
|PIN_RXP_EP_3
|D85_SOC_PCIE_TX0N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|V1
|PIN_RE_CH1
|D90_NAND_CH1_RE_ P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V2
|PIN_REB_CH1
|D90_NAND_CH1_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V3
|PIN_CE1_CH1
|S50_/NAND_CH2_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V4
|PIN_CE0_CH1
|S50_/NAND_CH2_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V5
|PIN_ALE_CH1
|S50_NAND_CH1_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V6
|PIN_CLE_CH1
|S50_NAND_CH1_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V7
|VSS_V7
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|V8
|VSS_V8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|V9
|VSS_V9
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|V10
|VDDQMIO_V10
|1.2V_FC_VDDQMIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|V11
|VDDQMIO_V11
|1.2V_FC_VDDQMIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|V12
|VDDQMIO_V12
|1.2V_FC_VDDQMIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|V13
|PIN_TEST[13]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|V14
|PIN_TEST[8]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|V15
|PIN_TEST[5]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|V16
|PIN_TEST[7]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|V17
|AVDD18_PLL
|1.8V_FC_AVDD
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|V18
|PIN_TEST[0]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|V19
|PIN_JT0_TMS
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|V20
|VSS_V20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|V21
|PIN_TXN_EP_3
|D85_SOC_PCIE_RX0P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V22
|PIN_TXP_EP_3
|D85_SOC_PCIE_RX0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V23
|VSS_V23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|V24
|VSS_V24
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|V25
|VSS_V25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|W1
|PIN_AD_CH1[7]
|S50_NAND_CH1_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|W2
|PIN_AD_CH1[6]
|S50_NAND_CH1_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|W3
|VSS_W3
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|W4
|PIN_AD_CH1[5]
|S50_NAND_CH1_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|W5
|PIN_WE_CH1
|NAND_CH1_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|W6
|PIN_CE2_CH1
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W7
|PIN_CE3_CH1
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W8
|VSS_W8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|W9
|VSS_W9
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|W10
|VSS_W10
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|W11
|VSS_W11
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|W12
|PIN_TEST[15]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W13
|PIN_TEST[9]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W14
|PIN_TEST[3]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W15
|VSS_W15
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|W16
|PIN_TEST[12]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W17
|PIN_TEST[6]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W18
|PIN_TEST[1]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W19
|PIN_CTS
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|W20
|PIN_RTS
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W21
|VSS_W21
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|W22
|VSS_W22
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|W23
|VSS_W23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|W24
|PIN_RXN_RC0
|D85_FC_RX0N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|W25
|PIN_RXP_RC0
|D85_FC_RX0P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|Y1
|PIN_DQSB_CH1
|D90_NAND_CH1_DQS_ P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|Y2
|PIN_DQS_CH1
|D90_NAND_CH1_DQS_ N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|Y3
|PIN_AD_CH1[4]
|S50_NAND_CH1_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|Y4
|PIN_AD_CH1[3]
|S50_NAND_CH1_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|Y5
|PIN_AD_CH1[2]
|S50_NAND_CH1_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|Y6
|VSS_Y6
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|Y7
|PIN_WP
|S50_/NAND_WP
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|Y8
|VSS_Y8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|Y9
|VSS_Y9
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|Y10
|VSS_Y10
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|Y11
|VSS_Y11
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|Y12
|VSS_Y12
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|Y13
|PIN_TEST[16]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|Y14
|PIN_TEST[11]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|Y15
|PIN_TEST[10]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|Y16
|PIN_TEST[14]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|Y17
|PIN_TEST[4]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|Y18
|PIN_TEST[2]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|Y19
|PIN_GPIO_0
|FC_MANU_MODE_SEL
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|Y20
|VSS_Y20
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|Y21
|PIN_TXN_RC0
|D85_FC_TX0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|Y22
|PIN_TXP_RC0
|D85_FC_TX0P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|Y23
|VSS_Y23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|Y24
|VSS_Y24
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|Y25
|VSS_Y25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AA1
|PIN_AD_CH1[1]
|S50_NAND_CH1_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AA2
|PIN_AD_CH1[0]
|S50_NAND_CH1_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AA3
|VSS_AA3
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AA4
|PIN_CLE_CH0
|S50_NAND_CH0_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AA5
|PIN_CE2_CH0
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AA6
|PIN_CE3_CH0
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AA7
|VSS_AA7
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AA8
|VSS_AA8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AA9
|VSS_AA9
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AA10
|VSS_AA10
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AA11
|VSS_AA11
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AA12
|PIN_VREFSMIO
|1.2V_FC_VDDQMIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AA13
|VSS_AA13
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AA14
|PIN_GPIO_7
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AA15
|PIN_SOC_V_RST
|/FC_RESET
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AA16
|PIN_GPIO_6
|PCIE_PEDET
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AA17
|PIN_GPIO_5
|3.3V_FC_VDDQ_MISC
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AA18
|PIN_GPIO_4
|3.3V_FC_VDDQ_MISC
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AA19
|PIN_GPIO_2
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AA20
|PIN_F_CS_N
|/FC_SPI_CS
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AA21
|VSS_AA21
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AA22
|VSS_AA22
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AA23
|VSS_AA23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AA24
|PIN_REFCLK_P_0
|D100G_FC_PCIE_CLK_P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AA25
|PIN_REFCLK_N_0
|D100G_FC_PCIE_CLK_N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AB1
|PIN_CE1_CH0
|S50_/NAND_CH2_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB2
|PIN_CE0_CH0
|S50_/NAND_CH2_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB3
|PIN_ALE_CH0
|S50_NAND_CH0_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB4
|PIN_AD_CH0[5]
|S50_NAND_CH0_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AB5
|PIN_AD_CH0[3]
|S50_NAND_CH0_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AB6
|VSS_AB6
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AB7
|PIN_M_A[15]
|S50_FC_DDR_A15
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB8
|PIN_M_A[11]
|S50_FC_DDR_A11
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB9
|PIN_M_A[8]
|S50_FC_DDR_A8
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB10
|PIN_M_A[4]
|S50_FC_DDR_A4
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB11
|PIN_M_ALERT_N
|S50_/FC_DDR_ALERTN
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB12
|PIN_DDR_CAL
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AB13
|PIN_M_ODT[0]
|S50_FC_DDR_ODT0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB14
|PIN_M_CS_N[0]
|S50_FC_DDR_CS0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB15
|PIN_M_D[7]
|S50_FC_DDR_D7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AB16
|PIN_M_D[6]
|S50_FC_DDR_D6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AB17
|PIN_M_D[2]
|S50_FC_DDR_D2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AB18
|PIN_M_D[1]
|S50_FC_DDR_D1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AB19
|PIN_M_DM
|S50_FC_DDR_DM
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB20
|PIN_GPIO_1
|FC_BOOT_CPU_SEL
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AB21
|PIN_F_Q
|SSB_SPIM_MISO
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB22
|PIN_JT0_DI
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AB23
|VSS_AB23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AB24
|VSS_AB24
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AB25
|VSS_AB25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AC1
|PIN_REB_CH0
|D90_NAND_CH0_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AC2
|PIN_RE_CH0
|D90_NAND_CH0_RE_P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AC3
|VSS_AC3
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AC4
|PIN_AD_CH0[4]
|S50_NAND_CH0_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AC5
|PIN_AD_CH0[2]
|S50_NAND_CH0_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AC6
|VSS_AC6
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AC7
|PIN_M_A[14]
|S50_FC_DDR_A14
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AC8
|VSS_AC8
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AC9
|PIN_M_A[7]
|S50_FC_DDR_A7
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AC10
|PIN_M_A[3]
|S50_FC_DDR_A3
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AC11
|VSS_AC11
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AC12
|PIN_M_PAR
|S50_FC_DDR_PAR
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AC13
|VSS_AC13
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AC14
|PIN_M_CS_N[1]
|N/C
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|No Connection
|-
|AC15
|PIN_M_WE_N
|S50_FC_DDR_WEN
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AC16
|VSS_AC16
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AC17
|PIN_M_D[3]
|S50_FC_DDR_D3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AC18
|VSS_AC18
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AC19
|PIN_M_D[0]
|S50_FC_DDR_D0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AC20
|PIN_GPIO_3
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AC21
|PIN_F_SPI_INT
|/FC_SPI_S_INT
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AC22
|PIN_JT0_TRSTN
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AC23
|VSS_AC23
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AC24
|PIN_XTLOUT
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AC25
|PIN_XTLIN
|S50G_FC_SYSCLK
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AD1
|VSS_AD1
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AD2
|PIN_WE_CH0
|S50_NANO_CH0_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AD3
|PIN_AD_CH0[7]
|S50_NAND_CH0_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AD4
|PIN_DQSB_CH0
|D90_NAND_CH0_DQS_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AD5
|PIN_AD_CH0[0]
|S50_NAND_CH0_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AD6
|VSS_AD6
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AD7
|PIN_M_A[13]
|S50_FC_DDR_A13
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AD8
|PIN_M_A[9]
|S50_FC_DDR_A9
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AD9
|PIN_M_A[6]
|S50_FC_DDR_A6
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AD10
|PIN_M_A[2]
|S50_FC_DDR_A2
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AD11
|PIN_M_BA[2]
|S50_FC_DDR_BA2
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AD12
|PIN_M_BA[0]
|S50_FC_DDR_BA0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AD13
|PIN_M_ODT[1]
|N/C
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|No Connection
|-
|AD14
|PIN_M_CKE[0]
|S50_FC_DDR_CKE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AD15
|PIN_M_CAS_N
|S50_/FC_DDR_CASN
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AD16
|PIN_M_CLOCK[0]
|D90_FC_DDR_CLOCK0_P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AD17
|PIN_M_D[4]
|S50_FC_DDR_D4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AD18
|PIN_M_DQS_P[0]
|D90_FC_DDR_DQS0_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AD19
|VSS_AD19
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AD20
|PIN_RX2
|FC_UART2_RX
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AD21
|PIN_TX
|FC_UART1_TX
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AD22
|PIN_F_D
|SSB_SPIM_MOSI
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AD23
|PIN_CLK_REQ_N_0
|/FC_CLK_REQ_N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AD24
|PIN_ANA_TP
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AD25
|VSS_AD25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AE1
|VSS_AE1
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AE2
|VSS_AE2
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AE3
|PIN_AD_CH0[6]
|S50_NAND_CH0_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AE4
|PIN_DQS_CH0
|D90_NAND_CH0_DQS_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AE5
|PIN_AD_CH0[1]
|S50_NAND_CH0_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AE6
|VSS_AE6
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AE7
|PIN_M_A[12]
|S50_FC_DDR_A12
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AE8
|PIN_M_A[10]
|S50_FC_DDR_A10
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AE9
|PIN_M_A[5]
|S50_FC_DDR_A5
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AE10
|PIN_M_A[1]
|S50_FC_DDR_A1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AE11
|PIN_M_A[0]
|S50_FC_DDR_A0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AE12
|PIN_M_BA[1]
|S50_FC_DDR_BA1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AE13
|PIN_M_RST_N
|NS50_/FC_DDR_RSTN
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AE14
|PIN_M_CKE[1]
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AE15
|PIN_M_RAS_N
|S50_/FC_DDR_RASN
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AE16
|PIN_M_CLOCK_N[0]
|D90_FC_DDR_CLOCK0_N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AE17
|PIN_M_D[5]
|S50_FC_DDR_D5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AE18
|PIN_M_DQS_N[0]
|D90_FC_DDR_DQS0_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AE19
|VSS_AE19
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AE20
|PIN_TX2
|FC_UART2_TX
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AE21
|PIN_RX
|FC_UART1_RX
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AE22
|PIN_F_CLK
|SSB_SPIM_CLK
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AE23
|PIN_JT0_DO
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AE24
|VSS_AE24
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|AE25
|VSS_AE25
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|}


= Pictures =
= Pictures =


[[File:CXD90062GG.jpeg]]<br>
[[File:CXD90062GG.jpeg|253x253px]]<br>
[[File:CXD90062GG2.jpeg]]
[[File:CXD90062GG2.jpeg|253x253px]]<br>
[[File:50980106477 3117f2d5c0 o.jpg|253x253px]]
[[File:CXD90062GG_Proto.png|253x253px]]
 
== Sources ==
https://www.flickr.com/photos/130561288@N04/albums/72157718290760702

Latest revision as of 08:21, 20 December 2024

  • NVME Controller, Codename Titania


Pinout[edit | edit source]

Pad Internal Name External Name Type Description
A1 VSS_A1 GND Input Ground
A2 VSS_A2 GND Input Ground
A3 PIN_REB_CH6 D90_NAND_CH6_RE_ N S50_/ Output
A4 PIN_CLE_CH6 S50_NAND_CH6_CLE Output
A5 PIN_AD_CH7[1] S50_NAND_CH7_AD1 Others
A6 PIN_DQSB_CH7 D90_NAND_CH7_DQS_N Others
A7 PIN_AD_CH7[7] S50_NAND_CH7_AD7 Others
A8 PIN_REB_CH7 D90_NAND_CH7_RE_ N S50_/ Output
A9 PIN_AD_CH8[1] S50_NAND_CH8_AD1 Others
A10 PIN_DQS_CH8 D90_NAND_CH8_DQS_P Others
A11 PIN_AD_CH8[7] S50_NAND_CH8_AD7 Others
A12 PIN_REB_CH8 D90_NAND_CH8_RE_ N S50_/ Output
A13 PIN_DQS_CH9 D90_NAND_CH9_DQS_P Others
A14 PIN_AD_CH9[7] S50_NAND_CH9_AD7 Others
A15 PIN_REB_CH9 D90_NAND_CH9_RE_ N S50_/ Output
A16 PIN_DQSB_CH10 D90_NAND_CH10_DQS_N Others
A17 PIN_AD_CH10[4] S50_NAND_CH10_AD4 Others
A18 PIN_REB_CH10 D90_NAND_CH10_RE_ N S50_/ Output
A19 PIN_AD_CH11[0] S50_NAND_CH11_AD0 Others
A20 PIN_DQSB_CH11 D90_NAND_CH11_DQS_N Others
A21 PIN_AD_CH11[6] S50_NAND_CH11_AD6 Others
A22 PIN_RE_CH11 D90_NAND_CH11_RE_ P Output
A23 PIN_CLE_CH11 S50_NAND_CH11_CLE Output
A24 VSS_A24 GND Input Ground
A25 VSS_A25 GND Input Ground
B1 VSS_B1 GND Input Ground
B2 PIN_AD_CH6[6] S50_NAND_CH6_AD6 Others
B3 PIN_RE_CH6 D90_NAND_CH6_RE_ P Output
B4 PIN_ALE_CH6 S50_NAND_CH6_ALE Output
B5 PIN_AD_CH7[0] S50_NAND_CH7_AD0 Others
B6 PIN_DQS_CH7 D90_NAND_CH7_DQS_P Others
B7 PIN_AD_CH7[6] S50_NAND_CH7_AD6 Others
B8 PIN_RE_CH7 D90_NAND_CH7_RE_ P Output
B9 PIN_AD_CH8[0] S50_NAND_CH8_AD0 Others
B10 PIN_DQSB_CH8 D90_NAND_CH8_DQS_N Others
B11 PIN_AD_CH8[6] S50_NAND_CH8_AD6 Others
B12 PIN_RE_CH8 D90_NAND_CH8_RE_ P Output
B13 PIN_DQSB_CH9 D90_NAND_CH9_DQS_N Others
B14 PIN_AD_CH9[6] S50_NAND_CH9_AD6 Others
B15 PIN_RE_CH9 D90_NAND_CH9_RE_ P Output
B16 PIN_DQS_CH10 D90_NAND_CH10_DQS_P Others
B17 PIN_AD_CH10[5] S50_NAND_CH10_AD5 Others
B18 PIN_RE_CH10 D90_NAND_CH10_RE_ P Output
B19 PIN_AD_CH11[1] S50_NAND_CH11_AD1 Others
B20 PIN_DQS_CH11 D90_NAND_CH11_DQS_P Others
B21 PIN_AD_CH11[7] S50_NAND_CH11_AD7 Others
B22 PIN_REB_CH11 D90_NAND_CH11_RE_ N S50_/ Output
B23 VSS_B23 GND Input Ground
B24 VSS_B24 GND Input Ground
B25 VSS_B25 GND Input Ground
C1 PIN_DQSB_CH6 D90_NAND_CH6_DQS_N Others
C2 PIN_DQS_CH6 D90_NAND_CH6_DQS_P Others
C3 VSS_C3 GND Input Ground
C4 PIN_AD_CH6[7] S50_NAND_CH6_AD7 Others
C5 PIN_CE0_CH6 S50_/NAND_CH6_CE0 Output
C6 VSS_C6 GND Input Ground
C7 PIN_AD_CH7[5] S50_NAND_CH7_AD5 Others
C8 VSS_C8 GND Input Ground
C9 PIN_CE1_CH7 S50_/NAND_CH7_CE1 Output
C10 PIN_AD_CH8[4] S50_NAND_CH8_AD4 Others
C11 VSS_C11 GND Input Ground
C12 PIN_CE1_CH8 S50_/NAND_CH8_CE1 Output
C13 PIN_AD_CH9[3] S50_NAND_CH9_AD3 Others
C14 VSS_C14 GND Input Ground
C15 PIN_CLE_CH9 S50_NAND_CH9_CLE Output
C16 PIN_AD_CH10[0] S50_NAND_CH10_AD0 Others
C17 VSS_C17 GND Input Ground
C18 PIN_CLE_CH10 S50_NAND_CH10_CLE Output
C19 PIN_AD_CH11[2] S50_NAND_CH11_AD2 Others
C20 PIN_WE_CH11 NAND_CH11_WE Output
C21 VSS_C21 GND Input Ground
C22 VSS_C22 GND Input Ground
C23 VSS_C23 GND Input Ground
C24 PIN_RXN_RC1_0 D85_M2_PCIE_RX0N Input
C25 PIN_RXP_RC1_0 D85_M2_PCIE_RX0P Input
D1 PIN_AD_CH6[3] S50_NAND_CH6_AD3 Others
D2 PIN_AD_CH6[2] S50_NAND_CH6_AD2 Others
D3 PIN_AD_CH6[5] S50_NAND_CH6_AD5 Others
D4 PIN_AD_CH6[4] S50_NAND_CH6_AD4 Others
D5 PIN_WE_CH6 NAND_CH6_WE Output
D6 PIN_AD_CH7[2] S50_NAND_CH7_AD2 Others
D7 PIN_AD_CH7[4] S50_NAND_CH7_AD4 Others
D8 PIN_CLE_CH7 S50_NAND_CH7_CLE Output
D9 PIN_CE0_CH7 S50_/NAND_CH7_CE0 Output
D10 PIN_AD_CH8[3] S50_NAND_CH8_AD3 Others
D11 PIN_AD_CH8[5] S50_NAND_CH8_AD5 Others
D12 PIN_CE0_CH8 S50_/NAND_CH8_CE0 Output
D13 PIN_AD_CH9[2] S50_NAND_CH9_AD2 Others
D14 PIN_AD_CH9[5] S50_NAND_CH9_AD5 Others
D15 PIN_ALE_CH9 S50_NAND_CH9_ALE Output
D16 PIN_AD_CH10[1] S50_NAND_CH10_AD1 Others
D17 PIN_AD_CH10[6] S50_NAND_CH10_AD6 Others
D18 PIN_ALE_CH10 S50_NAND_CH10_ALE Output
D19 PIN_AD_CH11[3] S50_NAND_CH11_AD3 Others
D20 VSS_D20 GND Input Ground
D21 PIN_TXN_RC1_0 D85_M2_PCIE_TX0N Output
D22 PIN_TXP_RC1_0 D85_M2_PCIE_TX0P Output
D23 VSS_D23 GND Input Ground
D24 VSS_D24 GND Input Ground
D25 VSS_D25 GND Input Ground
E1 PIN_RE_CH5 D90_NAND_CH5_RE_ P Output
E2 PIN_REB_CH5 D90_NAND_CH5_RE_ N S50_/ Output
E3 VSS_E3 GND Input Ground
E4 PIN_AD_CH6[1] S50_NAND_CH6_AD1 Others
E5 PIN_AD_CH6[0] S50_NAND_CH6_AD0 Others
E6 PIN_CE1_CH6 S50_/NAND_CH6_CE1 Output
E7 PIN_AD_CH7[3] S50_NAND_CH7_AD3 Others
E8 PIN_WE_CH7 NAND_CH7_WE Output
E9 PIN_ALE_CH7 S50_NAND_CH9_ALE Output
E10 PIN_AD_CH8[2] S50_NAND_CH8_AD2 Others
E11 PIN_WE_CH8 NAND_CH8_WE Output
E12 PIN_ALE_CH8 S50_NAND_CH8_ALE Output
E13 PIN_AD_CH9[1] S50_NAND_CH9_AD1 Others
E14 PIN_AD_CH9[4] S50_NAND_CH9_AD4 Others
E15 PIN_CE0_CH9 S50_/NAND_CH9_CE0 Output
E16 PIN_AD_CH10[2] S50_NAND_CH10_AD2 Others
E17 PIN_AD_CH10[7] S50_NAND_CH10_AD7 Others
E18 PIN_CE0_CH10 S50_/NAND_CH10_CE0 Output
E19 PIN_AD_CH11[5] S50_NAND_CH11_AD5 Others
E20 PIN_ALE_CH11 S50_NAND_CH11_ALE Output
E21 VSS_E21 GND Input Ground
E22 VSS_E22 GND Input Ground
E23 VSS_E23 GND Input Ground
E24 PIN_RXN_RC1_1 D85_M2_PCIE_RX1N Input
E25 PIN_RXP_RC1_1 D85_M2_PCIE_RX1P Input
F1 PIN_AD_CH5[4] S50_NAND_CH5_AD4 Others
F2 PIN_AD_CH5[5] S50_NAND_CH5_AD5 Others
F3 PIN_CLE_CH5 S50_NAND_CH5_CLE Output
F4 PIN_ALE_CH5 S50_NAND_CH5_ALE Output
F5 PIN_CE0_CH5 S50_/NAND_CH5_CE0 Output
F6 PIN_CE2_CH6 Not connected
F7 PIN_CE3_CH6 Not connected
F8 PIN_CE3_CH7 Not connected
F9 PIN_CE2_CH7 Not connected
F10 VSS_F10 GND Input Ground
F11 PIN_CE2_CH8 Not connected
F12 PIN_CLE_CH8 S50_NAND_CH8_CLE Output
F13 PIN_AD_CH9[0] S50_NAND_CH9_AD0 Others
F14 PIN_WE_CH9 NAND_CH9_WE Output
F15 PIN_CE1_CH9 S50_/NAND_CH9_CE1 Output
F16 PIN_AD_CH10[3] S50_NAND_CH10_AD3 Others
F17 PIN_WE_CH10 NAND_CH10_WE Output
F18 PIN_CE1_CH10 S50_/NAND_CH10_CE1 Output
F19 PIN_AD_CH11[4] S50_NAND_CH11_AD4 Others
F20 VSS_F20 GND Input Ground
F21 PIN_TXN_RC1_1 D85_M2_PCIE_TX1N Output
F22 PIN_TXP_RC1_1 D85_M2_PCIE_TX1P Output
F23 VSS_F23 GND Input Ground
F24 VSS_F24 GND Input Ground
F25 VSS_F25 GND Input Ground
G1 PIN_DQS_CH5 D90_NAND_CH5_DQS_P Others
G2 PIN_DQSB_CH5 D90_NAND_CH5_DQS_N Others
G3 PIN_AD_CH5[6] S50_NAND_CH5_AD6 Others
G4 PIN_AD_CH5[7] S50_NAND_CH5_AD7 Others
G5 PIN_WE_CH5 NAND_CH5_WE Output
G6 PIN_CE1_CH5 S50_/NAND_CH5_CE1 Output
G7 VSS_G7 GND Input Ground
G8 VSS_G8 GND Input Ground
G9 VSS_G9 GND Input Ground
G10 VSS_G10 GND Input Ground
G11 PIN_CE3_CH8 Not connected
G12 VSS_G12 GND Input Ground
G13 VSS_G13 GND Input Ground
G14 PIN_CE3_CH9 Not connected
G15 PIN_CE2_CH9 Not connected
G16 VSS_G16 GND Input Ground
G17 PIN_CE2_CH10 Not connected
G18 PIN_CE3_CH10 Not connected
G19 PIN_CE0_CH11 S50_/NAND_CH11_CE0 Output
G20 PIN_CE1_CH11 S50_/NAND_CH11_CE1 Output
G21 VSS_G21 GND Input Ground
G22 VSS_G22 GND Input Ground
G23 VSS_G23 GND Input Ground
G24 PIN_RXN_RC1_2 D85_M2_PCIE_RX2N Input
G25 PIN_RXP_RC1_2 D85_M2_PCIE_RX2P Input
H1 PIN_AD_CH5[0] S50_NAND_CH5_AD0 Others
H2 PIN_AD_CH5[1] S50_NAND_CH5_AD1 Others
H3 VSS_H3 GND Input Ground
H4 PIN_AD_CH5[2] S50_NAND_CH5_AD2 Others
H5 PIN_AD_CH5[3] S50_NAND_CH5_AD3 Others
H6 PIN_CE2_CH5 Not connected
H7 PIN_CE3_CH5 Not connected
H8 VSS_H8 GND Input Ground
H9 VSS_H9 GND Input Ground
H10 VSS_H10 GND Input Ground
H11 VSS_H11 GND Input Ground
H12 VSS_H12 GND Input Ground
H13 PIN_VREF_NF[1] 1.2V_FC_VDDQFIO Input
H14 VSS_H14 GND Input Ground
H15 VSS_H15 GND Input Ground
H16 VSS_H16 GND Input Ground
H17 VSS_H17 GND Input Ground
H18 PIN_CE3_CH11 Not connected
H19 PIN_CE2_CH11 Not connected
H20 VSS_H20 GND Input Ground
H21 PIN_TXN_RC1_2 D85_M2_PCIE_TX2N Output
H22 PIN_TXP_RC1_2 D85_M2_PCIE_TX2P Output
H23 VSS_H23 GND Input Ground
H24 VSS_H24 GND Input Ground
H25 VSS_H25 GND Input Ground
J1 PIN_REB_CH4 D90_NAND_CH4_RE_ N S50_/ Output
J2 PIN_RE_CH4 D90_NAND_CH4_RE_ P Output
J3 PIN_CLE_CH4 S50_NAND_CH4_CLE Output
J4 PIN_ALE_CH4 S50_NAND_CH4_ALE Output
J5 PIN_CE0_CH4 S50_/NAND_CH4_CE0 Output
J6 PIN_CE1_CH4 S50_/NAND_CH4_CE1 Output
J7 PIN_CE3_CH4 Not connected
J8 VSS_J8 GND Input Ground
J9 VSS_J9 GND Input Ground
J10 VDDOFIO_J10 1.2V_FC_VDDQFIO Input
J11 VDDOFIO_J11 1.2V_FC_VDDQFIO Input
J12 VDDOFIO_J12 1.2V_FC_VDDQFIO Input
J13 VSS_J13 GND Input Ground
J14 VDDOFIO_J14 1.2V_FC_VDDQFIO Input
J15 VDDOFIO_J15 1.2V_FC_VDDQFIO Input
J16 VDDOFIO_J16 1.2V_FC_VDDQFIO Input
J17 VSS_J17 GND Input Ground
J18 VSS_J18 GND Input Ground
J19 VSS_J19 GND Input Ground
J20 VSS_J20 GND Input Ground
J21 VSS_J21 GND Input Ground
J22 VSS_J22 GND Input Ground
J23 VSS_J23 GND Input Ground
J24 PIN_RXN_RC1_3 D85_M2_PCIE_RX3N Input
J25 PIN_RXP_RC1_3 D85_M2_PCIE_RX3P Input
K1 PIN_AD_CH4[4] S50_NAND_CH4_AD4 Others
K2 PIN_AD_CH4[5] S50_NAND_CH4_AD5 Others
K3 VSS_K3 GND Input Ground
K4 PIN_AD_CH4[6] S50_NAND_CH4_AD6 Others
K5 PIN_AD_CH4[7] S50_NAND_CH4_AD7 Others
K6 PIN_WE_CH4 NAND_CH4_WE Output
K7 PIN_CE2_CH4 Not connected
K8 VSS_K8 GND Input Ground
K9 VSS_K9 GND Input Ground
K10 VDD_K10 0.8V_FC_VDD Input
K11 VDD_K11 0.8V_FC_VDD Input
K12 VSS_K12 GND Input Ground
K13 VSS_K13 GND Input Ground
K14 VDD_K14 0.8V_FC_VDD Input
K15 VDD_K15 0.8V_FC_VDD Input
K16 VSS_K16 GND Input Ground
K17 VSS_K17 GND Input Ground
K18 VSS_K18 GND Input Ground
K19 VSS_K19 GND Input Ground
K20 VSS_K20 GND Input Ground
K21 PIN_TXN_RC1_3 D85_M2_PCIE_TX3N Output
K22 PIN_TXP_RC1_3 D85_M2_PCIE_TX3P Output
K23 VSS_K23 GND Input Ground
K24 VSS_K24 GND Input Ground
K25 VSS_K25 GND Input Ground
L1 PIN_DQS_CH4 D90_NAND_CH4_DQS_P Others
L2 PIN_DQSB_CH4 D90_NAND_CH4_DQS_N Others
L3 PIN_AD_CH4[3] S50_NAND_CH4_AD3 Others
L4 PIN_AD_CH4[2] S50_NAND_CH4_AD2 Others
L5 PIN_AD_CH4[1] S50_NAND_CH4_AD1 Others
L6 PIN_AD_CH4[0] S50_NAND_CH4_AD0 Others
L7 VSS_L7 GND Input Ground
L8 VSS_L8 GND Input Ground
L9 VDDOFIO_L9 1.2V_FC_VDDQFIO Input
L10 VSS_L10 GND Input Ground
L11 VSS_L11 GND Input Ground
L12 VDD_L12 0.8V_FC_VDD Input
L13 VDD_L13 0.8V_FC_VDD Input
L14 VSS_L14 GND Input Ground
L15 VSS_L15 GND Input Ground
L16 VDD_L16 0.8V_FC_VDD Input
L17 AVDD18_PCIE_L17 1.8V_FC_AVDD Input
L18 VSS_L18 GND Input Ground
L19 VSS_L19 GND Input Ground
L20 VSS_L20 GND Input Ground
L21 VSS_L21 GND Input Ground
L22 VSS_L22 GND Input Ground
L23 VSS_L23 GND Input Ground
L24 PIN_RXN_EP_0 D85_SOC_PCIE_TX3P Input
L25 PIN_RXP_EP_0 D85_SOC_PCIE_TX3N Input
M1 PIN_REB_CH3 D90_NAND_CH3_RE_ N S50_/ Output
M2 PIN_RE_CH3 D90_NAND_CH3_RE_ P Output
M3 PIN_CE1_CH3 S50_/NAND_CH3_CE1 Output
M4 PIN_CE0_CH3 S50_/NAND_CH3_CE0 Output
M5 PIN_ALE_CH3 S50_NAND_CH3_ALE Output
M6 PIN_CLE_CH3 S50_NAND_CH3_CLE Output
M7 PIN_CE2_CH3 Not connected
M8 PIN_CAL_NF S50_/NAND_WP Output
M9 VDDOFIO_M9 1.2V_FC_VDDQFIO Input
M10 VDD_M10 0.8V_FC_VDD Input
M11 VDD_M11 0.8V_FC_VDD Input
M12 VSS_M12 GND Input Ground
M13 VSS_M13 GND Input Ground
M14 VDD_M14 0.8V_FC_VDD Input
M15 VDD_M15 0.8V_FC_VDD Input
M16 VSS_M16 GND Input Ground
M17 AVDD18_PCIE_M17 1.8V_FC_AVDD Input
M18 VSS_M18 GND Input Ground
M19 VSS_M19 GND Input Ground
M20 VSS_M20 GND Input Ground
M21 PIN_TXN_EP_0 D85_SOC_PCIE_RX3P Output
M22 PIN_TXP_EP_0 D85_SOC_PCIE_RX3N Output
M23 VSS_M23 GND Input Ground
M24 VSS_M24 GND Input Ground
M25 VSS_M25 GND Input Ground
N1 PIN_AD_CH3[7] S50_NAND_CH3_AD7 Others
N2 PIN_AD_CH3[6] S50_NAND_CH3_AD6 Others
N3 VSS_N3 GND Input Ground
N4 PIN_AD_CH3[5] S50_NAND_CH3_AD5 Others
N5 PIN_AD_CH3[4] S50_NAND_CH3_AD4 Others
N6 PIN_WE_CH3 NAND_CH3_WE Output
N7 PIN_CE3_CH3 Not connected
N8 PIN_VREF_NF[0] 1.2V_FC_VDDQFIO Input
N9 VSS_N9 GND Input Ground
N10 VSS_N10 GND Input Ground
N11 VSS_N11 GND Input Ground
N12 VDD_N12 0.8V_FC_VDD Input
N13 VDD_N13 0.8V_FC_VDD Input
N14 VSS_N14 GND Input Ground
N15 VSS_N15 GND Input Ground
N16 VDD_N16 0.8V_FC_VDD Input
N17 VSS_N17 GND Input Ground
N18 VSS_N18 GND Input Ground
N19 VSS_N19 GND Input Ground
N20 VSS_N20 GND Input Ground
N21 VSS_N21 GND Input Ground
N22 VSS_N22 GND Input Ground
N23 VSS_N23 GND Input Ground
N24 PIN_RXN_EP_1 D85_SOC_PCIE_TX2P Input
N25 PIN_RXP_EP_1 D85_SOC_PCIE_TX2N Input
P1 PIN_DQSB_CH3 D90_NAND_CH3_DQS_N Others
P2 PIN_DQS_CH3 D90_NAND_CH3_DQS_P Others
P3 PIN_AD_CH3[3] S50_NAND_CH3_AD3 Others
P4 PIN_AD_CH3[2] S50_NAND_CH3_AD2 Others
P5 PIN_AD_CH3[1] S50_NAND_CH3_AD1 Others
P6 PIN_AD_CH3[0] S50_NAND_CH3_AD0 Others
P7 VSS_P7 GND Input Ground
P8 VSS_P8 GND Input Ground
P9 VDDOFIO_P9 1.2V_FC_VDDQFIO Input
P10 VDD_P10 0.8V_FC_VDD Input
P11 VDD_P11 0.8V_FC_VDD Input
P12 VSS_P12 GND Input Ground
P13 VSS_P13 GND Input Ground
P14 VDD_P14 0.8V_FC_VDD Input
P15 VDD_P15 0.8V_FC_VDD Input
P16 VSS_P16 GND Input Ground
P17 AVDD18_PCIE_P17 1.8V_FC_AVDD Input
P18 VSS_P18 GND Input Ground
P19 VSS_P19 GND Input Ground
P20 VSS_P20 GND Input Ground
P21 PIN_TXN_EP_1 D85_SOC_PCIE_RX2P Output
P22 PIN_TXP_EP_1 D85_SOC_PCIE_RX2N Output
P23 VSS_P23 GND Input Ground
P24 VSS_P24 GND Input Ground
P25 VSS_P25 GND Input Ground
R1 PIN_REB_CH2 D90_NAND_CH2_RE_ N S50_/ Output
R2 PIN_RE_CH2 D90_NAND_CH2_RE_ P Output
R3 PIN_CE1_CH2 S50_/NAND_CH2_CE1 Output
R4 PIN_CE0_CH2 S50_/NAND_CH2_CE0 Output
R5 PIN_ALE_CH2 S50_NAND_CH2_ALE Output
R6 PIN_CLE_CH2 S50_NAND_CH2_CLE Output
R7 PIN_CE2_CH2 Not connected
R8 VSS_R8 GND Input Ground
R9 VDDOFIO_R9 1.2V_FC_VDDQFIO Input
R10 VSS_R10 GND Input Ground
R11 VSS_R11 GND Input Ground
R12 VDD_R12 0.8V_FC_VDD Input
R13 VDD_R13 0.8V_FC_VDD Input
R14 VSS_R14 GND Input Ground
R15 VSS_R15 GND Input Ground
R16 VDD_R16 0.8V_FC_VDD Input
R17 AVDD18_PCIE_R17 1.8V_FC_AVDD Input
R18 VSS_R18 GND Input Ground
R19 VSS_R19 GND Input Ground
R20 VSS_R20 GND Input Ground
R21 VSS_R21 GND Input Ground
R22 VSS_R22 GND Input Ground
R23 VSS_R23 GND Input Ground
R24 PIN_RXN_EP_2 D85_SOC_PCIE_TX1P Input
R25 PIN_RXP_EP_2 D85_SOC_PCIE_TX1N Input
T1 PIN_AD_CH2[7] S50_NAND_CH2_AD7 Others
T2 PIN_AD_CH2[6] S50_NAND_CH2_AD6 Others
T3 VSS_T3 GND Input Ground
T4 PIN_AD_CH2[5] S50_NAND_CH2_AD5 Others
T5 PIN_AD_CH2[4] S50_NAND_CH2_AD4 Others
T6 PIN_WE_CH2 NAND_CH2_WE Output
T7 PIN_CE3_CH2 Not connected
T8 VSS_T8 GND Input Ground
T9 VDDOFIO_T9 1.2V_FC_VDDQFIO Input
T10 VDD_T10 0.8V_FC_VDD Input
T11 VDD_T11 0.8V_FC_VDD Input
T12 VSS_T12 GND Input Ground
T13 VDDO_MISC 3.3V_FC_VDDQ_MISC Input
T14 VDD_T14 0.8V_FC_VDD Input
T15 VDD_T15 0.8V_FC_VDD Input
T16 VSS_T16 GND Input Ground
T17 PIN_ISET GND Input Ground
T18 VSS_T18 GND Input Ground
T19 PIN_PERSTN PCIE_PERSTN Output
T20 VSS_T20 GND Input Ground
T21 PIN_TXN_EP_2 D85_SOC_PCIE_RX1P Output
T22 PIN_TXP_EP_2 D85_SOC_PCIE_RX1N Output
T23 VSS_T23 GND Input Ground
T24 VSS_T24 GND Input Ground
T25 VSS_T25 GND Input Ground
U1 PIN_DQSB_CH2 D90_NAND_CH2_DQS_N Others
U2 PIN_DQS_CH2 D90_NAND_CH2_DQS_P Others
U3 PIN_AD_CH2[3] S50_NAND_CH2_AD3 Others
U4 PIN_AD_CH2[2] S50_NAND_CH2_AD2 Others
U5 PIN_AD_CH2[1] S50_NAND_CH2_AD1 Others
U6 PIN_AD_CH2[0] S50_NAND_CH2_AD0 Others
U7 VSS_U7 GND Input Ground
U8 VSS_U8 GND Input Ground
U9 VSS_U9 GND Input Ground
U10 VDDQMIO_U10 1.2V_FC_VDDQMIO Input
U11 VDDQMIO_U11 1.2V_FC_VDDQMIO Input
U12 VDDQMIO_U12 1.2V_FC_VDDQMIO Input
U13 AVDD18_PLLA 1.8V_FC_AVDD Input
U14 VSS_U14 GND Input Ground
U15 VDDO_MISC_1P8V 1.8V_FC_AVDD Input
U16 AVDD18_EFUSE 1.8V_FC_AVDD Input
U17 VSS_U17 GND Input Ground
U18 AVDD18_ANA 1.8V_FC_AVDD Input
U19 PIN_JT0_CLK Not connected
U20 VSS_U20 GND Input Ground
U21 VSS_U21 GND Input Ground
U22 VSS_U22 GND Input Ground
U23 VSS_U23 GND Input Ground
U24 PIN_RXN_EP_3 D85_SOC_PCIE_TX0P Input
U25 PIN_RXP_EP_3 D85_SOC_PCIE_TX0N Input
V1 PIN_RE_CH1 D90_NAND_CH1_RE_ P Output
V2 PIN_REB_CH1 D90_NAND_CH1_RE_ N S50_/ Output
V3 PIN_CE1_CH1 S50_/NAND_CH2_CE1 Output
V4 PIN_CE0_CH1 S50_/NAND_CH2_CE0 Output
V5 PIN_ALE_CH1 S50_NAND_CH1_ALE Output
V6 PIN_CLE_CH1 S50_NAND_CH1_CLE Output
V7 VSS_V7 GND Input Ground
V8 VSS_V8 GND Input Ground
V9 VSS_V9 GND Input Ground
V10 VDDQMIO_V10 1.2V_FC_VDDQMIO Input
V11 VDDQMIO_V11 1.2V_FC_VDDQMIO Input
V12 VDDQMIO_V12 1.2V_FC_VDDQMIO Input
V13 PIN_TEST[13] Not connected
V14 PIN_TEST[8] Not connected
V15 PIN_TEST[5] Not connected
V16 PIN_TEST[7] Not connected
V17 AVDD18_PLL 1.8V_FC_AVDD Input
V18 PIN_TEST[0] Not connected
V19 PIN_JT0_TMS Not connected
V20 VSS_V20 GND Input Ground
V21 PIN_TXN_EP_3 D85_SOC_PCIE_RX0P Output
V22 PIN_TXP_EP_3 D85_SOC_PCIE_RX0N Output
V23 VSS_V23 GND Input Ground
V24 VSS_V24 GND Input Ground
V25 VSS_V25 GND Input Ground
W1 PIN_AD_CH1[7] S50_NAND_CH1_AD7 Others
W2 PIN_AD_CH1[6] S50_NAND_CH1_AD6 Others
W3 VSS_W3 GND Input Ground
W4 PIN_AD_CH1[5] S50_NAND_CH1_AD5 Others
W5 PIN_WE_CH1 NAND_CH1_WE Output
W6 PIN_CE2_CH1 Not connected
W7 PIN_CE3_CH1 Not connected
W8 VSS_W8 GND Input Ground
W9 VSS_W9 GND Input Ground
W10 VSS_W10 GND Input Ground
W11 VSS_W11 GND Input Ground
W12 PIN_TEST[15] Not connected
W13 PIN_TEST[9] Not connected
W14 PIN_TEST[3] Not connected
W15 VSS_W15 GND Input Ground
W16 PIN_TEST[12] Not connected
W17 PIN_TEST[6] Not connected
W18 PIN_TEST[1] Not connected
W19 PIN_CTS GND Input Ground
W20 PIN_RTS Not connected
W21 VSS_W21 GND Input Ground
W22 VSS_W22 GND Input Ground
W23 VSS_W23 GND Input Ground
W24 PIN_RXN_RC0 D85_FC_RX0N Input
W25 PIN_RXP_RC0 D85_FC_RX0P Input
Y1 PIN_DQSB_CH1 D90_NAND_CH1_DQS_ P Others
Y2 PIN_DQS_CH1 D90_NAND_CH1_DQS_ N Others
Y3 PIN_AD_CH1[4] S50_NAND_CH1_AD4 Others
Y4 PIN_AD_CH1[3] S50_NAND_CH1_AD3 Others
Y5 PIN_AD_CH1[2] S50_NAND_CH1_AD2 Others
Y6 VSS_Y6 GND Input Ground
Y7 PIN_WP S50_/NAND_WP Output
Y8 VSS_Y8 GND Input Ground
Y9 VSS_Y9 GND Input Ground
Y10 VSS_Y10 GND Input Ground
Y11 VSS_Y11 GND Input Ground
Y12 VSS_Y12 GND Input Ground
Y13 PIN_TEST[16] Not connected
Y14 PIN_TEST[11] Not connected
Y15 PIN_TEST[10] Not connected
Y16 PIN_TEST[14] Not connected
Y17 PIN_TEST[4] Not connected
Y18 PIN_TEST[2] Not connected
Y19 PIN_GPIO_0 FC_MANU_MODE_SEL Others
Y20 VSS_Y20 GND Input Ground
Y21 PIN_TXN_RC0 D85_FC_TX0N Output
Y22 PIN_TXP_RC0 D85_FC_TX0P Output
Y23 VSS_Y23 GND Input Ground
Y24 VSS_Y24 GND Input Ground
Y25 VSS_Y25 GND Input Ground
AA1 PIN_AD_CH1[1] S50_NAND_CH1_AD1 Others
AA2 PIN_AD_CH1[0] S50_NAND_CH1_AD0 Others
AA3 VSS_AA3 GND Input Ground
AA4 PIN_CLE_CH0 S50_NAND_CH0_CLE Output
AA5 PIN_CE2_CH0 Not connected
AA6 PIN_CE3_CH0 Not connected
AA7 VSS_AA7 GND Input Ground
AA8 VSS_AA8 GND Input Ground
AA9 VSS_AA9 GND Input Ground
AA10 VSS_AA10 GND Input Ground
AA11 VSS_AA11 GND Input Ground
AA12 PIN_VREFSMIO 1.2V_FC_VDDQMIO Input
AA13 VSS_AA13 GND Input Ground
AA14 PIN_GPIO_7 Not connected
AA15 PIN_SOC_V_RST /FC_RESET Input
AA16 PIN_GPIO_6 PCIE_PEDET Input
AA17 PIN_GPIO_5 3.3V_FC_VDDQ_MISC Input
AA18 PIN_GPIO_4 3.3V_FC_VDDQ_MISC Input
AA19 PIN_GPIO_2 Not connected
AA20 PIN_F_CS_N /FC_SPI_CS Input
AA21 VSS_AA21 GND Input Ground
AA22 VSS_AA22 GND Input Ground
AA23 VSS_AA23 GND Input Ground
AA24 PIN_REFCLK_P_0 D100G_FC_PCIE_CLK_P Input
AA25 PIN_REFCLK_N_0 D100G_FC_PCIE_CLK_N Input
AB1 PIN_CE1_CH0 S50_/NAND_CH2_CE1 Output
AB2 PIN_CE0_CH0 S50_/NAND_CH2_CE0 Output
AB3 PIN_ALE_CH0 S50_NAND_CH0_ALE Output
AB4 PIN_AD_CH0[5] S50_NAND_CH0_AD5 Others
AB5 PIN_AD_CH0[3] S50_NAND_CH0_AD3 Others
AB6 VSS_AB6 GND Input Ground
AB7 PIN_M_A[15] S50_FC_DDR_A15 Output
AB8 PIN_M_A[11] S50_FC_DDR_A11 Output
AB9 PIN_M_A[8] S50_FC_DDR_A8 Output
AB10 PIN_M_A[4] S50_FC_DDR_A4 Output
AB11 PIN_M_ALERT_N S50_/FC_DDR_ALERTN Output
AB12 PIN_DDR_CAL GND Input Ground
AB13 PIN_M_ODT[0] S50_FC_DDR_ODT0 Output
AB14 PIN_M_CS_N[0] S50_FC_DDR_CS0N Output
AB15 PIN_M_D[7] S50_FC_DDR_D7 Others
AB16 PIN_M_D[6] S50_FC_DDR_D6 Others
AB17 PIN_M_D[2] S50_FC_DDR_D2 Others
AB18 PIN_M_D[1] S50_FC_DDR_D1 Others
AB19 PIN_M_DM S50_FC_DDR_DM Output
AB20 PIN_GPIO_1 FC_BOOT_CPU_SEL Others
AB21 PIN_F_Q SSB_SPIM_MISO Output
AB22 PIN_JT0_DI Not connected
AB23 VSS_AB23 GND Input Ground
AB24 VSS_AB24 GND Input Ground
AB25 VSS_AB25 GND Input Ground
AC1 PIN_REB_CH0 D90_NAND_CH0_RE_ N S50_/ Output
AC2 PIN_RE_CH0 D90_NAND_CH0_RE_P Output
AC3 VSS_AC3 GND Input Ground
AC4 PIN_AD_CH0[4] S50_NAND_CH0_AD4 Others
AC5 PIN_AD_CH0[2] S50_NAND_CH0_AD2 Others
AC6 VSS_AC6 GND Input Ground
AC7 PIN_M_A[14] S50_FC_DDR_A14 Output
AC8 VSS_AC8 GND Input Ground
AC9 PIN_M_A[7] S50_FC_DDR_A7 Output
AC10 PIN_M_A[3] S50_FC_DDR_A3 Output
AC11 VSS_AC11 GND Input Ground
AC12 PIN_M_PAR S50_FC_DDR_PAR Output
AC13 VSS_AC13 GND Input Ground
AC14 PIN_M_CS_N[1] N/C Not connected No Connection
AC15 PIN_M_WE_N S50_FC_DDR_WEN Output
AC16 VSS_AC16 GND Input Ground
AC17 PIN_M_D[3] S50_FC_DDR_D3 Others
AC18 VSS_AC18 GND Input Ground
AC19 PIN_M_D[0] S50_FC_DDR_D0 Others
AC20 PIN_GPIO_3 Not connected
AC21 PIN_F_SPI_INT /FC_SPI_S_INT Output
AC22 PIN_JT0_TRSTN Not connected
AC23 VSS_AC23 GND Input Ground
AC24 PIN_XTLOUT Not connected
AC25 PIN_XTLIN S50G_FC_SYSCLK Input
AD1 VSS_AD1 GND Input Ground
AD2 PIN_WE_CH0 S50_NANO_CH0_WE Output
AD3 PIN_AD_CH0[7] S50_NAND_CH0_AD7 Others
AD4 PIN_DQSB_CH0 D90_NAND_CH0_DQS_N Others
AD5 PIN_AD_CH0[0] S50_NAND_CH0_AD0 Others
AD6 VSS_AD6 GND Input Ground
AD7 PIN_M_A[13] S50_FC_DDR_A13 Output
AD8 PIN_M_A[9] S50_FC_DDR_A9 Output
AD9 PIN_M_A[6] S50_FC_DDR_A6 Output
AD10 PIN_M_A[2] S50_FC_DDR_A2 Output
AD11 PIN_M_BA[2] S50_FC_DDR_BA2 Output
AD12 PIN_M_BA[0] S50_FC_DDR_BA0 Output
AD13 PIN_M_ODT[1] N/C Not connected No Connection
AD14 PIN_M_CKE[0] S50_FC_DDR_CKE0 Output
AD15 PIN_M_CAS_N S50_/FC_DDR_CASN Output
AD16 PIN_M_CLOCK[0] D90_FC_DDR_CLOCK0_P Output
AD17 PIN_M_D[4] S50_FC_DDR_D4 Others
AD18 PIN_M_DQS_P[0] D90_FC_DDR_DQS0_P Others
AD19 VSS_AD19 GND Input Ground
AD20 PIN_RX2 FC_UART2_RX Input
AD21 PIN_TX FC_UART1_TX Output
AD22 PIN_F_D SSB_SPIM_MOSI Input
AD23 PIN_CLK_REQ_N_0 /FC_CLK_REQ_N Output
AD24 PIN_ANA_TP Not connected
AD25 VSS_AD25 GND Input Ground
AE1 VSS_AE1 GND Input Ground
AE2 VSS_AE2 GND Input Ground
AE3 PIN_AD_CH0[6] S50_NAND_CH0_AD6 Others
AE4 PIN_DQS_CH0 D90_NAND_CH0_DQS_P Others
AE5 PIN_AD_CH0[1] S50_NAND_CH0_AD1 Others
AE6 VSS_AE6 GND Input Ground
AE7 PIN_M_A[12] S50_FC_DDR_A12 Output
AE8 PIN_M_A[10] S50_FC_DDR_A10 Output
AE9 PIN_M_A[5] S50_FC_DDR_A5 Output
AE10 PIN_M_A[1] S50_FC_DDR_A1 Output
AE11 PIN_M_A[0] S50_FC_DDR_A0 Output
AE12 PIN_M_BA[1] S50_FC_DDR_BA1 Output
AE13 PIN_M_RST_N NS50_/FC_DDR_RSTN Output
AE14 PIN_M_CKE[1] GND Input Ground
AE15 PIN_M_RAS_N S50_/FC_DDR_RASN Output
AE16 PIN_M_CLOCK_N[0] D90_FC_DDR_CLOCK0_N Output
AE17 PIN_M_D[5] S50_FC_DDR_D5 Others
AE18 PIN_M_DQS_N[0] D90_FC_DDR_DQS0_N Others
AE19 VSS_AE19 GND Input Ground
AE20 PIN_TX2 FC_UART2_TX Output
AE21 PIN_RX FC_UART1_RX Input
AE22 PIN_F_CLK SSB_SPIM_CLK Input
AE23 PIN_JT0_DO Not connected
AE24 VSS_AE24 GND Input Ground
AE25 VSS_AE25 GND Input Ground

Pictures[edit | edit source]

CXD90062GG.jpeg
CXD90062GG2.jpeg
50980106477 3117f2d5c0 o.jpg CXD90062GG Proto.png

Sources[edit | edit source]

https://www.flickr.com/photos/130561288@N04/albums/72157718290760702

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