MN864739: Difference between revisions
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m (→IC Pin Out) |
(Added some pin descriptions) |
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(One intermediate revision by one other user not shown) | |||
Line 36: | Line 36: | ||
|D85_SOC_DP0_TX0P | |D85_SOC_DP0_TX0P | ||
| | | | ||
| | |DP In, Lane0+ | ||
|- | |- | ||
|5 | |5 | ||
Line 42: | Line 42: | ||
|D85_SOC_DP0_TX0M | |D85_SOC_DP0_TX0M | ||
| | | | ||
| | |DP In, Lane0- | ||
|- | |- | ||
|6 | |6 | ||
Line 66: | Line 66: | ||
|D85_SOC_DP0_TX1P | |D85_SOC_DP0_TX1P | ||
| | | | ||
| | |DP In, Lane1+ | ||
|- | |- | ||
|10 | |10 | ||
Line 72: | Line 72: | ||
|D85_SOC_DP0_TX1M | |D85_SOC_DP0_TX1M | ||
| | | | ||
| | |DP In, Lane1- | ||
|- | |- | ||
|11 | |11 | ||
Line 84: | Line 84: | ||
|D85_SOC_DP0_TX2P | |D85_SOC_DP0_TX2P | ||
| | | | ||
| | |DP In, Lane2+ | ||
|- | |- | ||
|13 | |13 | ||
Line 90: | Line 90: | ||
|D85_SOC_DP0_TX2M | |D85_SOC_DP0_TX2M | ||
| | | | ||
| | |DP In, Lane2- | ||
|- | |- | ||
|14 | |14 | ||
Line 114: | Line 114: | ||
|D85_SOC_DP0_TX3P | |D85_SOC_DP0_TX3P | ||
| | | | ||
| | |DP In, Lane3+ | ||
|- | |- | ||
|18 | |18 | ||
Line 120: | Line 120: | ||
|D85_SOC_DP0_TX3M | |D85_SOC_DP0_TX3M | ||
| | | | ||
| | |DP In, Lane3- | ||
|- | |- | ||
|19 | |19 | ||
Line 150: | Line 150: | ||
|/HDMI_IRQ | |/HDMI_IRQ | ||
| | | | ||
| | |Hdmi Interrupt | ||
|- | |- | ||
|24 | |24 | ||
Line 168: | Line 168: | ||
|HDMI_I2C_SDA | |HDMI_I2C_SDA | ||
| | | | ||
| | |Host I2C data | ||
|- | |- | ||
|27 | |27 | ||
Line 174: | Line 174: | ||
|HDMI_I2C_SCL | |HDMI_I2C_SCL | ||
| | | | ||
| | |Host I2C clock | ||
|- | |- | ||
|28 | |28 | ||
Line 374: | Line 374: | ||
|Ground | |Ground | ||
|- | |- | ||
|61 | |||
|PVDD18 | |||
|1.8V_HDMI_POWER | |||
| | | | ||
| | | | ||
|- | |||
|62 | |||
|AMON1 | |||
|GND | |||
|[[File:IC-Pin-in.png|frameless]] | |||
|Ground | |||
|- | |||
|63 | |||
|TEST2 | |||
| | | | ||
| | | | ||
| | |Test Pad Only (CL3020) | ||
|- | |- | ||
|64 | |||
|VDD09_64 | |||
|0.9V_HDMI | |||
| | | | ||
| | | | ||
|- | |||
|65 | |||
|VSS_65 | |||
|GND | |||
|[[File:IC-Pin-in.png|frameless]] | |||
|Ground | |||
|- | |||
|66 | |||
|SYSCLK | |||
|S50G_HDMI_SYSCLK | |||
| | | | ||
|27Mhz core clock input | |||
|- | |||
|67 | |||
|VDD18_67 | |||
|1.8V_HDMI | |||
| | | | ||
| | | | ||
|- | |- | ||
|68 | |||
|TEST3 | |||
| | | | ||
| | | | ||
|Test Pad Only (CL3015) | |||
|- | |||
|69 | |||
|TEST4 | |||
| | | | ||
| | | | ||
| | |Test Pad Only (CL3013) | ||
|- | |||
|70 | |||
|VSS_70 | |||
|GND | |||
|[[File:IC-Pin-in.png|frameless]] | |||
|Ground | |||
|- | |- | ||
|71 | |||
|VDD09_71 | |||
|0.9V_HDMI | |||
| | | | ||
| | | | ||
|- | |||
|72 | |||
|PTEST1 | |||
|GND | |||
|[[File:IC-Pin-in.png|frameless]] | |||
|Ground | |||
|- | |||
|73 | |||
|PTEST2 | |||
|GND | |||
|[[File:IC-Pin-in.png|frameless]] | |||
|Ground | |||
|- | |||
|74 | |||
|DPHPD_IRQ | |||
|SOC_DP0_HPD | |||
| | | | ||
|DP Hotplug interrupt | |||
|- | |||
|75 | |||
|VDD09_75 | |||
|0.9V_HDMI | |||
| | | | ||
| | | | ||
|- | |- | ||
|76 | |||
|VSS_76 | |||
|GND | |||
|[[File:IC-Pin-in.png|frameless]] | |||
|Ground | |||
|- | |||
|77 | |||
|AMON2 | |||
|GND | |||
|[[File:IC-Pin-in.png|frameless]] | |||
|Ground | |||
|- | |||
|78 | |||
|DPAUXP | |||
|D85_SOC_DP0_AUX_P | |||
| | | | ||
|DP in, Aux+ | |||
|- | |||
|79 | |||
|DPAUXM | |||
|D85_SOC_DP0_AUX_N | |||
| | | | ||
| | |DP in, Aux- | ||
|- | |||
|80 | |||
|AVDD18RX_80 | |||
|1.8V_HDMI_ANA_RX | |||
| | | | ||
| | | |
Latest revision as of 10:01, 13 December 2024
- HDMI Chip
- Codename FLAVA