MN864739: Difference between revisions

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m (pin updates)
(Added some pin descriptions)
 
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Line 36: Line 36:
|D85_SOC_DP0_TX0P
|D85_SOC_DP0_TX0P
|
|
|
|DP In, Lane0+
|-
|-
|5
|5
Line 42: Line 42:
|D85_SOC_DP0_TX0M
|D85_SOC_DP0_TX0M
|
|
|
|DP In, Lane0-
|-
|-
|6
|6
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|D85_SOC_DP0_TX1P
|D85_SOC_DP0_TX1P
|
|
|
|DP In, Lane1+
|-
|-
|10
|10
Line 72: Line 72:
|D85_SOC_DP0_TX1M
|D85_SOC_DP0_TX1M
|
|
|
|DP In, Lane1-
|-
|-
|11
|11
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|D85_SOC_DP0_TX2P
|D85_SOC_DP0_TX2P
|
|
|
|DP In, Lane2+
|-
|-
|13
|13
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|D85_SOC_DP0_TX2M
|D85_SOC_DP0_TX2M
|
|
|
|DP In, Lane2-
|-
|-
|14
|14
Line 114: Line 114:
|D85_SOC_DP0_TX3P
|D85_SOC_DP0_TX3P
|
|
|
|DP In, Lane3+
|-
|-
|18
|18
Line 120: Line 120:
|D85_SOC_DP0_TX3M
|D85_SOC_DP0_TX3M
|
|
|
|DP In, Lane3-
|-
|-
|19
|19
Line 150: Line 150:
|/HDMI_IRQ
|/HDMI_IRQ
|
|
|
|Hdmi Interrupt
|-
|-
|24
|24
Line 168: Line 168:
|HDMI_I2C_SDA
|HDMI_I2C_SDA
|
|
|
|Host I2C data
|-
|-
|27
|27
Line 174: Line 174:
|HDMI_I2C_SCL
|HDMI_I2C_SCL
|
|
|
|Host I2C clock
|-
|-
|28
|28
|VDD18_28
|1.8V_HDMI
|
|
|
|
|-
|29
|VSS_29
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|30
|VDD09_30
|0.9V_HDMI
|
|
|
|
|-
|-
|29
|31
|PWRON
|HDMI_0.9V_PWRON
|
|
|
|
|-
|32
|NRESET
|/HDMI_RESET
|
|
|
|
|-
|-
|30
|33
|VSS_33
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|34
|VDD09_34
|0.9V_HDMI
|
|
|
|
|-
|35
|HPD
|HPD
|
|
|Pin 19 HDMI Port
|-
|36
|SDA
|DDC_DATA
|
|
|Pin 16 HDMI Port
|-
|-
|31
|37
|SCL
|DDC_CLK
|
|
|Pin 15 HDMI Port
|-
|38
|VDD09_38
|0.9V_HDMI
|
|
|
|
|-
|39
|CEC
|CEC
|
|
|Pin 13 HDMI Port
|-
|-
|32
|40
|TEST1
|1.8V_HDMI
|
|
|
|
|-
|41
|VSS_41
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|42
|AVDD09TX_42
|0.9V_HDMI_ANA_TX
|
|
|
|
|-
|-
|33
|43
|AVSSTX_43
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|44
|TX3M
|D100_FLV_TX_CKN
|
|Pin 12 HDMI Port
|-
|45
|TX3P
|D100_FLV_TX_CKP
|
|Pin 10 HDMI Port
|-
|46
|AVSSTX_46
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|47
|TX0M
|D100_FLV_TX_D0N
|
|
|Pin 9 HDMI Port
|-
|48
|TX0P
|D100_FLV_TX_D0P
|
|
|Pin 7 HDMI Port
|-
|49
|AVSSTX_49
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|50
|AVDD09TX_50
|0.9V_HDMI_ANA_TX
|
|
|
|
|-
|-
|34
|51
|AVSSTX_51
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|52
|TX1M
|D100_FLV_TX_D1N
|
|
|Pin 6 HDMI Port
|-
|53
|TX1P
|D100_FLV_TX_D1P
|
|
|Pin 4 HDMI Port
|-
|54
|AVSSTX_54
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|55
|TX2M
|D100_FLV_TX_D2N
|
|
|Pin 3 HDMI Port
|-
|56
|TX2P
|D100_FLV_TX_D2P
|
|
|Pin 1 HDMI Port
|-
|57
|AVSSTX_57
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|-
|35
|58
|AVDD09TX_58
|0.9V_HDMI_ANA_TX
|
|
|
|
|-
|59
|AVDD18TX
|1.8V_HDMI_ANA_TX
|
|
|
|
|-
|-
|36
|60
|PVSS
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|61
|PVDD18
|1.8V_HDMI_POWER
|
|
|
|
|-
|62
|AMON1
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|63
|TEST2
|
|
|
|
|Test Pad Only (CL3020)
|-
|-
|37
|64
|VDD09_64
|0.9V_HDMI
|
|
|
|-
|65
|VSS_65
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|66
|SYSCLK
|S50G_HDMI_SYSCLK
|
|
|27Mhz core clock input
|-
|67
|VDD18_67
|1.8V_HDMI
|
|
|
|
|-
|-
|38
|68
|TEST3
|
|
|
|
|Test Pad Only (CL3015)
|-
|69
|TEST4
|
|
|
|
|Test Pad Only (CL3013)
|-
|-
|39
|70
|VSS_70
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|71
|VDD09_71
|0.9V_HDMI
|
|
|
|
|-
|72
|PTEST1
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|73
|PTEST2
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|74
|DPHPD_IRQ
|SOC_DP0_HPD
|
|DP Hotplug interrupt
|-
|75
|VDD09_75
|0.9V_HDMI
|
|
|
|
|-
|-
|40
|76
|VSS_76
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|77
|AMON2
|GND
|[[File:IC-Pin-in.png|frameless]]
|Ground
|-
|78
|DPAUXP
|D85_SOC_DP0_AUX_P
|
|
|DP in, Aux+
|-
|79
|DPAUXM
|D85_SOC_DP0_AUX_N
|
|
|DP in, Aux-
|-
|80
|AVDD18RX_80
|1.8V_HDMI_ANA_RX
|
|
|
|

Latest revision as of 10:01, 13 December 2024

Panasonic MN864739
  • HDMI Chip
  • Codename FLAVA

IC Pin Out[edit | edit source]

Panasonic MN864739 Pin Out
Pad Internal Exterrnal Type Description
1 AVDD18RX_1 1.8V_HDMI_ANA_RX
2 AVDD09RX_2 0.9V_HDMI_ANA_RX
3 AVSSRX_3 GND IC-Pin-in.png Ground
4 DPLANE0P D85_SOC_DP0_TX0P DP In, Lane0+
5 DPLANE0M D85_SOC_DP0_TX0M DP In, Lane0-
6 AVSSRX_6 GND IC-Pin-in.png Ground
7 AVDD09RX_7 0.9V_HDMI_ANA_RX
8 AVSSRX_8 GND IC-Pin-in.png Ground
9 DPLANE1P D85_SOC_DP0_TX1P DP In, Lane1+
10 DPLANE1M D85_SOC_DP0_TX1M DP In, Lane1-
11 AVSSRX_11 GND IC-Pin-in.png Ground
12 DPLANE2P D85_SOC_DP0_TX2P DP In, Lane2+
13 DPLANE2M D85_SOC_DP0_TX2M DP In, Lane2-
14 AVSSRX_14 GND IC-Pin-in.png Ground
15 AVDD09RX_15 0.9V_HDMI_ANA_RX
16 AVSSRX_16 GND IC-Pin-in.png Ground
17 DPLANE3P D85_SOC_DP0_TX3P DP In, Lane3+
18 DPLANE3M D85_SOC_DP0_TX3M DP In, Lane3-
19 AVSSRX_19 GND IC-Pin-in.png Ground
20 AVDD09RX_20 0.9V_HDMI_ANA_RX
21 PTEST3 GND IC-Pin-in.png Ground
22 NTEST 1.8V_HDMI
23 NIRQ /HDMI_IRQ Hdmi Interrupt
24 VDD09STB 0.9V_HDMI_SB
25 VSS_25 GND IC-Pin-in.png Ground
26 HSDA HDMI_I2C_SDA Host I2C data
27 HSCL HDMI_I2C_SCL Host I2C clock
28 VDD18_28 1.8V_HDMI
29 VSS_29 GND IC-Pin-in.png Ground
30 VDD09_30 0.9V_HDMI
31 PWRON HDMI_0.9V_PWRON
32 NRESET /HDMI_RESET
33 VSS_33 GND IC-Pin-in.png Ground
34 VDD09_34 0.9V_HDMI
35 HPD HPD Pin 19 HDMI Port
36 SDA DDC_DATA Pin 16 HDMI Port
37 SCL DDC_CLK Pin 15 HDMI Port
38 VDD09_38 0.9V_HDMI
39 CEC CEC Pin 13 HDMI Port
40 TEST1 1.8V_HDMI
41 VSS_41 GND IC-Pin-in.png Ground
42 AVDD09TX_42 0.9V_HDMI_ANA_TX
43 AVSSTX_43 GND IC-Pin-in.png Ground
44 TX3M D100_FLV_TX_CKN Pin 12 HDMI Port
45 TX3P D100_FLV_TX_CKP Pin 10 HDMI Port
46 AVSSTX_46 GND IC-Pin-in.png Ground
47 TX0M D100_FLV_TX_D0N Pin 9 HDMI Port
48 TX0P D100_FLV_TX_D0P Pin 7 HDMI Port
49 AVSSTX_49 GND IC-Pin-in.png Ground
50 AVDD09TX_50 0.9V_HDMI_ANA_TX
51 AVSSTX_51 GND IC-Pin-in.png Ground
52 TX1M D100_FLV_TX_D1N Pin 6 HDMI Port
53 TX1P D100_FLV_TX_D1P Pin 4 HDMI Port
54 AVSSTX_54 GND IC-Pin-in.png Ground
55 TX2M D100_FLV_TX_D2N Pin 3 HDMI Port
56 TX2P D100_FLV_TX_D2P Pin 1 HDMI Port
57 AVSSTX_57 GND IC-Pin-in.png Ground
58 AVDD09TX_58 0.9V_HDMI_ANA_TX
59 AVDD18TX 1.8V_HDMI_ANA_TX
60 PVSS GND IC-Pin-in.png Ground
61 PVDD18 1.8V_HDMI_POWER
62 AMON1 GND IC-Pin-in.png Ground
63 TEST2 Test Pad Only (CL3020)
64 VDD09_64 0.9V_HDMI
65 VSS_65 GND IC-Pin-in.png Ground
66 SYSCLK S50G_HDMI_SYSCLK 27Mhz core clock input
67 VDD18_67 1.8V_HDMI
68 TEST3 Test Pad Only (CL3015)
69 TEST4 Test Pad Only (CL3013)
70 VSS_70 GND IC-Pin-in.png Ground
71 VDD09_71 0.9V_HDMI
72 PTEST1 GND IC-Pin-in.png Ground
73 PTEST2 GND IC-Pin-in.png Ground
74 DPHPD_IRQ SOC_DP0_HPD DP Hotplug interrupt
75 VDD09_75 0.9V_HDMI
76 VSS_76 GND IC-Pin-in.png Ground
77 AMON2 GND IC-Pin-in.png Ground
78 DPAUXP D85_SOC_DP0_AUX_P DP in, Aux+
79 DPAUXM D85_SOC_DP0_AUX_N DP in, Aux-
80 AVDD18RX_80 1.8V_HDMI_ANA_RX

Pictures[edit | edit source]

MN864739.png Panasonic MN864739 Proto.png

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