CXD90062GG: Difference between revisions
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= Pictures = | = Pictures = | ||
[[File:CXD90062GG.jpeg]]<br> | [[File:CXD90062GG.jpeg|253x253px]]<br> | ||
[[File:CXD90062GG2.jpeg]]<br> | [[File:CXD90062GG2.jpeg|253x253px]]<br> | ||
[[File:50980106477 3117f2d5c0 o.jpg| | [[File:50980106477 3117f2d5c0 o.jpg|253x253px]] | ||
[[File:CXD90062GG_Proto.png]] | [[File:CXD90062GG_Proto.png|253x253px]] | ||
== Sources == | == Sources == | ||
https://www.flickr.com/photos/130561288@N04/albums/72157718290760702 | https://www.flickr.com/photos/130561288@N04/albums/72157718290760702 | ||
Revision as of 23:49, 12 December 2024
NVME Controller
Pinout
| Pad | Internal Name | External Name | Type | Description |
|---|---|---|---|---|
| AA1 | PIN_AD_CH1[1] | S50_NAND_CH1_AD1 | 
|
|
| AA2 | PIN_AD_CH1[0] | S50_NAND_CH1_AD0 |
|
|
| AA4 | PIN_CLE_CH0 | S50_NAND_CH0_CLE | 
|
|
| AA5 | PIN_CE2_CH0 | 
|
||
| AA6 | PIN_CE3_CH0 |
|
||
| AA12 | PIN_VREFSMIO | 1.2V_FC_VDDQMIO | 
|
|
| AA14 | PIN_GPIO_7 |
|
||
| AA15 | PIN_SOC_V_RST | /FC_RESET |
|
|
| AA16 | PIN_GPIO_6 | PCIE_PEDET |
|
|
| AA17 | PIN_GPIO_5 | 3.3V_FC_VDDQ_MISC |
|
|
| AA18 | PIN_GPIO_4 | 3.3V_FC_VDDQ_MISC |
|
|
| AA19 | PIN_GPIO_2 |
|
||
| AA20 | PIN_F_CS_N | /FC_SPI_CS |
|
|
| AA24 | PIN_REFCLK_P_0 | D100G_FC_PCIE_CLK_P |
|
|
| AA25 | PIN_REFCLK_N_0 | D100G_FC_PCIE_CLK_N |
|
|
| AB1 | PIN_CE1_CH0 | S50_/NAND_CH2_CE1 |
|
|
| AB2 | PIN_CE0_CH0 | S50_/NAND_CH2_CE0 |
|
|
| AB3 | PIN_ALE_CH0 | S50_NAND_CH0_ALE |
|
|
| AB4 | PIN_AD_CH0[5] | S50_NAND_CH0_AD5 |
|
|
| AB5 | PIN_AD_CH0[3] | S50_NAND_CH0_AD3 |
|
|
| AB7 | PIN_M_A[15] | S50_FC_DDR_A15 |
|
|
| AB8 | PIN_M_A[11] | S50_FC_DDR_A11 |
|
|
| AB9 | PIN_M_A[8] | S50_FC_DDR_A8 |
|
|
| AB10 | PIN_M_A[4] | S50_FC_DDR_A4 |
|
|
| AB11 | PIN_M_ALERT_N | S50_/FC_DDR_ALERTN |
|
|
| AB12 | PIN_DDR_CAL | GND |
|
Ground |
| AB13 | PIN_M_ODT[0] | S50_FC_DDR_ODT0 |
|
|
| AB14 | PIN_M_CS_N[0] | S50_FC_DDR_CS0N |
|
|
| AB15 | PIN_M_D[7] | S50_FC_DDR_D7 |
|
|
| AB16 | PIN_M_D[6] | S50_FC_DDR_D6 |
|
|
| AB17 | PIN_M_D[2] | S50_FC_DDR_D2 |
|
|
| AB18 | PIN_M_D[1] | S50_FC_DDR_D1 |
|
|
| AB19 | PIN_M_DM | S50_FC_DDR_DM |
|
|
| AB20 | PIN_GPIO_1 | FC_BOOT_CPU_SEL |
|
|
| AB21 | PIN_F_Q | SSB_SPIM_MISO |
|
|
| AB22 | PIN_JT0_DI |
|
||
| AC1 | PIN_REB_CH0 | D90_NAND_CH0_RE_ N S50_/ |
|
|
| AC2 | PIN_RE_CH0 | D90_NAND_CH0_RE_P |
|
|
| AC4 | PIN_AD_CH0[4] | S50_NAND_CH0_AD4 |
|
|
| AC5 | PIN_AD_CH0[2] | S50_NAND_CH0_AD2 |
|
|
| AC7 | PIN_M_A[14] | S50_FC_DDR_A14 |
|
|
| AC9 | PIN_M_A[7] | S50_FC_DDR_A7 |
|
|
| AC10 | PIN_M_A[3] | S50_FC_DDR_A3 |
|
|
| AC12 | PIN_M_PAR | S50_FC_DDR_PAR |
|
|
| AC14 | PIN_M_CS_N[1] | N/C |
|
No Connection |
| AC15 | PIN_M_WE_N | S50_FC_DDR_WEN |
|
|
| AC17 | PIN_M_D[3] | S50_FC_DDR_D3 |
|
|
| AC19 | PIN_M_D[0] | S50_FC_DDR_D0 |
|
|
| AC20 | PIN_GPIO_3 |
|
||
| AC21 | PIN_F_SPI_INT | /FC_SPI_S_INT |
|
|
| AC22 | PIN_JT0_TRSTN |
|
||
| AC24 | PIN_XTLOUT |
|
||
| AC25 | PIN_XTLIN | S50G_FC_SYSCLK |
|
|
| AD2 | PIN_WE_CH0 | S50_NANO_CH0_WE |
|
|
| AD3 | PIN_AD_CH0[7] | S50_NAND_CH0_AD7 |
|
|
| AD4 | PIN_DQSB_CH0 | D90_NAND_CH0_DQS_N |
|
|
| AD5 | PIN_AD_CH0[0] | S50_NAND_CH0_AD0 |
|
|
| AD7 | PIN_M_A[13] | S50_FC_DDR_A13 |
|
|
| AD8 | PIN_M_A[9] | S50_FC_DDR_A9 |
|
|
| AD9 | PIN_M_A[6] | S50_FC_DDR_A6 |
|
|
| AD10 | PIN_M_A[2] | S50_FC_DDR_A2 |
|
|
| AD11 | PIN_M_BA[2] | S50_FC_DDR_BA2 |
|
|
| AD12 | PIN_M_BA[0] | S50_FC_DDR_BA0 |
|
|
| AD13 | PIN_M_ODT[1] | N/C |
|
No Connection |
| AD14 | PIN_M_CKE[0] | S50_FC_DDR_CKE0 |
|
|
| AD15 | PIN_M_CAS_N | S50_/FC_DDR_CASN |
|
|
| AD16 | PIN_M_CLOCK[0] | D90_FC_DDR_CLOCK0_P |
|
|
| AD17 | PIN_M_D[4] | S50_FC_DDR_D4 |
|
|
| AD18 | PIN_M_DQS_P[0] | D90_FC_DDR_DQS0_P |
|
|
| AD20 | PIN_RX2 | FC_UART2_RX |
|
|
| AD21 | PIN_TX | FC_UART1_TX |
|
|
| AD22 | PIN_F_D | SSB_SPIM_MOSI |
|
|
| AD23 | PIN_CLK_REQ_N_0 | /FC_CLK_REQ_N |
|
|
| AD24 | PIN_ANA_TP |
|
||
| AE3 | PIN_AD_CH0[6] | S50_NAND_CH0_AD6 |
|
|
| AE4 | PIN_DQS_CH0 | D90_NAND_CH0_DQS_P |
|
|
| AE5 | PIN_AD_CH0[1] | S50_NAND_CH0_AD1 |
|
|
| AE7 | PIN_M_A[12] | S50_FC_DDR_A12 |
|
|
| AE8 | PIN_M_A[10] | S50_FC_DDR_A10 |
|
|
| AE9 | PIN_M_A[5] | S50_FC_DDR_A5 |
|
|
| AE10 | PIN_M_A[1] | S50_FC_DDR_A1 |
|
|
| AE11 | PIN_M_A[0] | S50_FC_DDR_A0 |
|
|
| AE12 | PIN_M_BA[1] | S50_FC_DDR_BA1 |
|
|
| AE13 | PIN_M_RST_N | NS50_/FC_DDR_RSTN |
|
|
| AE14 | PIN_M_CKE[1] | GND |
|
Ground |
| AE15 | PIN_M_RAS_N | S50_/FC_DDR_RASN |
|
|
| AE16 | PIN_M_CLOCK_N[0] | D90_FC_DDR_CLOCK0_N |
|
|
| AE17 | PIN_M_D[5] | S50_FC_DDR_D5 |
|
|
| AE18 | PIN_M_DQS_N[0] | D90_FC_DDR_DQS0_N |
|
|
| AE20 | PIN_TX2 | FC_UART2_TX |
|
|
| AE21 | PIN_RX | FC_UART1_RX |
|
|
| AE22 | PIN_F_CLK | SSB_SPIM_CLK |
|
|
| AE23 | PIN_JT0_DO |
|
||
| C24 | PIN_RXN_RC1_0 | D85_M2_PCIE_RX0N |
|
|
| C25 | PIN_RXP_RC1_0 | D85_M2_PCIE_RX0P |
|
|
| D21 | PIN_TXN_RC1_0 | D85_M2_PCIE_TX0N |
|
|
| D22 | PIN_TXP_RC1_0 | D85_M2_PCIE_TX0P |
|
|
| E24 | PIN_RXN_RC1_1 | D85_M2_PCIE_RX1N |
|
|
| E25 | PIN_RXP_RC1_1 | D85_M2_PCIE_RX1P |
|
|
| F21 | PIN_TXN_RC1_1 | D85_M2_PCIE_TX1N |
|
|
| F22 | PIN_TXP_RC1_1 | D85_M2_PCIE_TX1P |
|
|
| G24 | PIN_RXN_RC1_2 | D85_M2_PCIE_RX2N |
|
|
| G25 | PIN_RXP_RC1_2 | D85_M2_PCIE_RX2P |
|
|
| H13 | PIN_VREF_NF[1] | 1.2V_FC_VDDQFIO |
|
|
| H21 | PIN_TXN_RC1_2 | D85_M2_PCIE_TX2N |
|
|
| H22 | PIN_TXP_RC1_2 | D85_M2_PCIE_TX2P |
|
|
| J24 | PIN_RXN_RC1_3 | D85_M2_PCIE_RX3N |
|
|
| J25 | PIN_RXP_RC1_3 | D85_M2_PCIE_RX3P |
|
|
| K21 | PIN_TXN_RC1_3 | D85_M2_PCIE_TX3N |
|
|
| K22 | PIN_TXP_RC1_3 | D85_M2_PCIE_TX3P |
|
|
| L24 | PIN_RXN_EP_0 | D85_SOC_PCIE_TX3P |
|
|
| L25 | PIN_RXP_EP_0 | D85_SOC_PCIE_TX3N |
|
|
| M8 | PIN_CAL_NF | S50_/NAND_WP |
|
|
| M21 | PIN_TXN_EP_0 | D85_SOC_PCIE_RX3P |
|
|
| M22 | PIN_TXP_EP_0 | D85_SOC_PCIE_RX3N |
|
|
| N8 | PIN_VREF_NF[0] | 1.2V_FC_VDDQFIO |
|
|
| N24 | PIN_RXN_EP_1 | D85_SOC_PCIE_TX2P |
|
|
| N25 | PIN_RXP_EP_1 | D85_SOC_PCIE_TX2N |
|
|
| P21 | PIN_TXN_EP_1 | D85_SOC_PCIE_RX2P |
|
|
| P22 | PIN_TXP_EP_1 | D85_SOC_PCIE_RX2N |
|
|
| R24 | PIN_RXN_EP_2 | D85_SOC_PCIE_TX1P |
|
|
| R25 | PIN_RXP_EP_2 | D85_SOC_PCIE_TX1N |
|
|
| T17 | PIN_ISET | GND |
|
Ground |
| T19 | PIN_PERSTN | PCIE_PERSTN |
|
|
| T21 | PIN_TXN_EP_2 | D85_SOC_PCIE_RX1P |
|
|
| T22 | PIN_TXP_EP_2 | D85_SOC_PCIE_RX1N |
|
|
| U19 | PIN_JT0_CLK |
|
||
| U24 | PIN_RXN_EP_3 | D85_SOC_PCIE_TX0P |
|
|
| U25 | PIN_RXP_EP_3 | D85_SOC_PCIE_TX0N |
|
|
| V1 | PIN_RE_CH1 | D90_NAND_CH1_RE_ P |
|
|
| V2 | PIN_REB_CH1 | D90_NAND_CH1_RE_ N S50_/ |
|
|
| V3 | PIN_CE1_CH1 | S50_/NAND_CH2_CE1 |
|
|
| V4 | PIN_CE0_CH1 | S50_/NAND_CH2_CE0 |
|
|
| V5 | PIN_ALE_CH1 | S50_NAND_CH1_ALE |
|
|
| V6 | PIN_CLE_CH1 | S50_NAND_CH1_CLE |
|
|
| V18 | PIN_TEST[0] |
|
||
| V13 | PIN_TEST[13] |
|
||
| V14 | PIN_TEST[8] |
|
||
| V15 | PIN_TEST[5] |
|
||
| V16 | PIN_TEST[7] |
|
||
| V19 | PIN_JT0_TMS |
|
||
| V21 | PIN_TXN_EP_3 | D85_SOC_PCIE_RX0P |
|
|
| V22 | PIN_TXP_EP_3 | D85_SOC_PCIE_RX0N |
|
|
| W1 | PIN_AD_CH1[7] | S50_NAND_CH1_AD7 |
|
|
| W2 | PIN_AD_CH1[6] | S50_NAND_CH1_AD6 |
|
|
| W4 | PIN_AD_CH1[5] | S50_NAND_CH1_AD5 |
|
|
| W5 | PIN_WE_CH1 | NAND_CH1_WE |
|
|
| W6 | PIN_CE2_CH1 |
|
||
| W7 | PIN_CE3_CH1 |
|
||
| W12 | PIN_TEST[15] |
|
||
| W13 | PIN_TEST[9] |
|
||
| W14 | PIN_TEST[3] |
|
||
| W16 | PIN_TEST[12] |
|
||
| W17 | PIN_TEST[6] |
|
||
| W18 | PIN_TEST[1] |
|
||
| W19 | PIN_CTS | GND |
|
Ground |
| W20 | PIN_RTS |
|
||
| W24 | PIN_RXN_RC0 | D85_FC_RX0N |
|
|
| W25 | PIN_RXP_RC0 | D85_FC_RX0P |
|
|
| Y1 | PIN_DQSB_CH1 | D90_NAND_CH1_DQS_ P |
|
|
| Y2 | PIN_DQS_CH1 | D90_NAND_CH1_DQS_ N |
|
|
| Y3 | PIN_AD_CH1[4] | S50_NAND_CH1_AD4 |
|
|
| Y4 | PIN_AD_CH1[3] | S50_NAND_CH1_AD3 |
|
|
| Y5 | PIN_AD_CH1[2] | S50_NAND_CH1_AD2 |
|
|
| Y7 | PIN_WP | S50_/NAND_WP |
|
|
| Y13 | PIN_TEST[16] |
|
||
| Y14 | PIN_TEST[11] |
|
||
| Y15 | PIN_TEST[10] |
|
||
| Y16 | PIN_TEST[14] |
|
||
| Y17 | PIN_TEST[4] |
|
||
| Y19 | PIN_GPIO_0 | FC_MANU_MODE_SEL |
|
|
| Y21 | PIN_TXN_RC0 | D85_FC_TX0N |
|
|
| Y18 | PIN_TEST[2] |
|
||
| Y22 | PIN_TXP_RC0 | D85_FC_TX0P |
|
Pictures
Sources
https://www.flickr.com/photos/130561288@N04/albums/72157718290760702