CXD90062GG: Difference between revisions

From PS5 Developer wiki
Jump to navigation Jump to search
(→‎Pinout: Added GPIO&TEST and UART, also reorganize alphabetically.)
(→‎Pinout: Added CH0,1)
Line 11: Line 11:
!Type
!Type
!Description
!Description
|-
|AA1
|PIN_AD_CH1[1]
|S50_NAND_CH1_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AA2
|PIN_AD_CH1[0]
|S50_NAND_CH1_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AA4
|PIN_CLE_CH0
|S50_NAND_CH0_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AA5
|PIN_CE2_CH0
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AA6
|PIN_CE3_CH0
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|-
|AA12
|AA12
Line 70: Line 100:
|D100G_FC_PCIE_CLK_N
|D100G_FC_PCIE_CLK_N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AB1
|PIN_CE1_CH0
|S50_/NAND_CH2_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB2
|PIN_CE0_CH0
|S50_/NAND_CH2_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB3
|PIN_ALE_CH0
|S50_NAND_CH0_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB4
|PIN_AD_CH0[5]
|S50_NAND_CH0_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AB5
|PIN_AD_CH0[3]
|S50_NAND_CH0_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|
|-
|-
Line 166: Line 226:
|
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AC1
|PIN_REB_CH0
|D90_NAND_CH0_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AC2
|PIN_RE_CH0
|D90_NAND_CH0_RE_P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AC4
|PIN_AD_CH0[4]
|S50_NAND_CH0_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AC5
|PIN_AD_CH0[2]
|S50_NAND_CH0_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|
|-
|-
Line 244: Line 328:
|S50G_FC_SYSCLK
|S50G_FC_SYSCLK
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AD2
|PIN_WE_CH0
|S50_NANO_CH0_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AD3
|PIN_AD_CH0[7]
|S50_NAND_CH0_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AD4
|PIN_DQSB_CH0
|D90_NAND_CH0_DQS_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AD5
|PIN_AD_CH0[0]
|S50_NAND_CH0_AD0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|
|-
|-
Line 346: Line 454:
|
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AE3
|PIN_AD_CH0[6]
|S50_NAND_CH0_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AE4
|PIN_DQS_CH0
|D90_NAND_CH0_DQS_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AE5
|PIN_AD_CH0[1]
|S50_NAND_CH0_AD1
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|
|-
|-
Line 501: Line 627:
|PIN_RXP_RC1_2
|PIN_RXP_RC1_2
|D85_M2_PCIE_RX2P
|D85_M2_PCIE_RX2P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|H13
|PIN_VREF_NF[1]
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|
Line 550: Line 682:
|D85_SOC_PCIE_TX3N
|D85_SOC_PCIE_TX3N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|M8
|PIN_CAL_NF
|S50_/NAND_WP
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|
|-
|-
Line 562: Line 700:
|D85_SOC_PCIE_RX3N
|D85_SOC_PCIE_RX3N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|N8
|PIN_VREF_NF[0]
|1.2V_FC_VDDQFIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|
|-
|-
Line 640: Line 784:
|D85_SOC_PCIE_TX0N
|D85_SOC_PCIE_TX0N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|V1
|PIN_RE_CH1
|D90_NAND_CH1_RE_ P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V2
|PIN_REB_CH1
|D90_NAND_CH1_RE_ N S50_/
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V3
|PIN_CE1_CH1
|S50_/NAND_CH2_CE1
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V4
|PIN_CE0_CH1
|S50_/NAND_CH2_CE0
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V5
|PIN_ALE_CH1
|S50_NAND_CH1_ALE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V6
|PIN_CLE_CH1
|S50_NAND_CH1_CLE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|
|-
|-
Line 688: Line 868:
|D85_SOC_PCIE_RX0N
|D85_SOC_PCIE_RX0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|W1
|PIN_AD_CH1[7]
|S50_NAND_CH1_AD7
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|W2
|PIN_AD_CH1[6]
|S50_NAND_CH1_AD6
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|W4
|PIN_AD_CH1[5]
|S50_NAND_CH1_AD5
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|W5
|PIN_WE_CH1
|NAND_CH1_WE
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|W6
|PIN_CE2_CH1
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W7
|PIN_CE3_CH1
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|
|-
|-
Line 748: Line 964:
|D85_FC_RX0P
|D85_FC_RX0P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|Y1
|PIN_DQSB_CH1
|D90_NAND_CH1_DQS_ P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|Y2
|PIN_DQS_CH1
|D90_NAND_CH1_DQS_ N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|Y3
|PIN_AD_CH1[4]
|S50_NAND_CH1_AD4
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|Y4
|PIN_AD_CH1[3]
|S50_NAND_CH1_AD3
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|Y5
|PIN_AD_CH1[2]
|S50_NAND_CH1_AD2
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|Y7
|PIN_WP
|S50_/NAND_WP
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|
|-
|-

Revision as of 20:57, 12 December 2024

NVME Controller


Pinout

Pad Internal Name External Name Type Description
AA1 PIN_AD_CH1[1] S50_NAND_CH1_AD1 Others
AA2 PIN_AD_CH1[0] S50_NAND_CH1_AD0 Others
AA4 PIN_CLE_CH0 S50_NAND_CH0_CLE Output
AA5 PIN_CE2_CH0 Not connected
AA6 PIN_CE3_CH0 Not connected
AA12 PIN_VREFSMIO 1.2V_FC_VDDQMIO Input
AA14 PIN_GPIO_7 Not connected
AA15 PIN_SOC_V_RST /FC_RESET Input
AA16 PIN_GPIO_6 PCIE_PEDET Input
AA17 PIN_GPIO_5 3.3V_FC_VDDQ_MISC Input
AA18 PIN_GPIO_4 3.3V_FC_VDDQ_MISC Input
AA19 PIN_GPIO_2 Not connected
AA20 PIN_F_CS_N /FC_SPI_CS Input
AA24 PIN_REFCLK_P_0 D100G_FC_PCIE_CLK_P Input
AA25 PIN_REFCLK_N_0 D100G_FC_PCIE_CLK_N Input
AB1 PIN_CE1_CH0 S50_/NAND_CH2_CE1 Output
AB2 PIN_CE0_CH0 S50_/NAND_CH2_CE0 Output
AB3 PIN_ALE_CH0 S50_NAND_CH0_ALE Output
AB4 PIN_AD_CH0[5] S50_NAND_CH0_AD5 Others
AB5 PIN_AD_CH0[3] S50_NAND_CH0_AD3 Others
AB7 PIN_M_A[15] S50_FC_DDR_A15 Output
AB8 PIN_M_A[11] S50_FC_DDR_A11 Output
AB9 PIN_M_A[8] S50_FC_DDR_A8 Output
AB10 PIN_M_A[4] S50_FC_DDR_A4 Output
AB11 PIN_M_ALERT_N S50_/FC_DDR_ALERTN Output
AB12 PIN_DDR_CAL GND Input Ground
AB13 PIN_M_ODT[0] S50_FC_DDR_ODT0 Output
AB14 PIN_M_CS_N[0] S50_FC_DDR_CS0N Output
AB15 PIN_M_D[7] S50_FC_DDR_D7 Others
AB16 PIN_M_D[6] S50_FC_DDR_D6 Others
AB17 PIN_M_D[2] S50_FC_DDR_D2 Others
AB18 PIN_M_D[1] S50_FC_DDR_D1 Others
AB19 PIN_M_DM S50_FC_DDR_DM Output
AB20 PIN_GPIO_1 FC_BOOT_CPU_SEL Others
AB21 PIN_F_Q SSB_SPIM_MISO Output
AB22 PIN_JT0_DI Not connected
AC1 PIN_REB_CH0 D90_NAND_CH0_RE_ N S50_/ Output
AC2 PIN_RE_CH0 D90_NAND_CH0_RE_P Output
AC4 PIN_AD_CH0[4] S50_NAND_CH0_AD4 Others
AC5 PIN_AD_CH0[2] S50_NAND_CH0_AD2 Others
AC7 PIN_M_A[14] S50_FC_DDR_A14 Output
AC9 PIN_M_A[7] S50_FC_DDR_A7 Output
AC10 PIN_M_A[3] S50_FC_DDR_A3 Output
AC12 PIN_M_PAR S50_FC_DDR_PAR Output
AC14 PIN_M_CS_N[1] N/C Not connected No Connection
AC15 PIN_M_WE_N S50_FC_DDR_WEN Output
AC17 PIN_M_D[3] S50_FC_DDR_D3 Others
AC19 PIN_M_D[0] S50_FC_DDR_D0 Others
AC20 PIN_GPIO_3 Not connected
AC21 PIN_F_SPI_INT /FC_SPI_S_INT Output
AC22 PIN_JT0_TRSTN Not connected
AC24 PIN_XTLOUT Not connected
AC25 PIN_XTLIN S50G_FC_SYSCLK Input
AD2 PIN_WE_CH0 S50_NANO_CH0_WE Output
AD3 PIN_AD_CH0[7] S50_NAND_CH0_AD7 Others
AD4 PIN_DQSB_CH0 D90_NAND_CH0_DQS_N Others
AD5 PIN_AD_CH0[0] S50_NAND_CH0_AD0 Others
AD7 PIN_M_A[13] S50_FC_DDR_A13 Output
AD8 PIN_M_A[9] S50_FC_DDR_A9 Output
AD9 PIN_M_A[6] S50_FC_DDR_A6 Output
AD10 PIN_M_A[2] S50_FC_DDR_A2 Output
AD11 PIN_M_BA[2] S50_FC_DDR_BA2 Output
AD12 PIN_M_BA[0] S50_FC_DDR_BA0 Output
AD13 PIN_M_ODT[1] N/C Not connected No Connection
AD14 PIN_M_CKE[0] S50_FC_DDR_CKE0 Output
AD15 PIN_M_CAS_N S50_/FC_DDR_CASN Output
AD16 PIN_M_CLOCK[0] D90_FC_DDR_CLOCK0_P Output
AD17 PIN_M_D[4] S50_FC_DDR_D4 Others
AD18 PIN_M_DQS_P[0] D90_FC_DDR_DQS0_P Others
AD20 PIN_RX2 FC_UART2_RX Input
AD21 PIN_TX FC_UART1_TX Output
AD22 PIN_F_D SSB_SPIM_MOSI Input
AD23 PIN_CLK_REQ_N_0 /FC_CLK_REQ_N Output
AD24 PIN_ANA_TP Not connected
AE3 PIN_AD_CH0[6] S50_NAND_CH0_AD6 Others
AE4 PIN_DQS_CH0 D90_NAND_CH0_DQS_P Others
AE5 PIN_AD_CH0[1] S50_NAND_CH0_AD1 Others
AE7 PIN_M_A[12] S50_FC_DDR_A12 Output
AE8 PIN_M_A[10] S50_FC_DDR_A10 Output
AE9 PIN_M_A[5] S50_FC_DDR_A5 Output
AE10 PIN_M_A[1] S50_FC_DDR_A1 Output
AE11 PIN_M_A[0] S50_FC_DDR_A0 Output
AE12 PIN_M_BA[1] S50_FC_DDR_BA1 Output
AE13 PIN_M_RST_N NS50_/FC_DDR_RSTN Output
AE14 PIN_M_CKE[1] GND Input Ground
AE15 PIN_M_RAS_N S50_/FC_DDR_RASN Output
AE16 PIN_M_CLOCK_N[0] D90_FC_DDR_CLOCK0_N Output
AE17 PIN_M_D[5] S50_FC_DDR_D5 Others
AE18 PIN_M_DQS_N[0] D90_FC_DDR_DQS0_N Others
AE20 PIN_TX2 FC_UART2_TX Output
AE21 PIN_RX FC_UART1_RX Input
AE22 PIN_F_CLK SSB_SPIM_CLK Input
AE23 PIN_JT0_DO Not connected
C24 PIN_RXN_RC1_0 D85_M2_PCIE_RX0N Input
C25 PIN_RXP_RC1_0 D85_M2_PCIE_RX0P Input
D21 PIN_TXN_RC1_0 D85_M2_PCIE_TX0N Output
D22 PIN_TXP_RC1_0 D85_M2_PCIE_TX0P Output
E24 PIN_RXN_RC1_1 D85_M2_PCIE_RX1N Input
E25 PIN_RXP_RC1_1 D85_M2_PCIE_RX1P Input
F21 PIN_TXN_RC1_1 D85_M2_PCIE_TX1N Output
F22 PIN_TXP_RC1_1 D85_M2_PCIE_TX1P Output
G24 PIN_RXN_RC1_2 D85_M2_PCIE_RX2N Input
G25 PIN_RXP_RC1_2 D85_M2_PCIE_RX2P Input
H13 PIN_VREF_NF[1] 1.2V_FC_VDDQFIO Input
H21 PIN_TXN_RC1_2 D85_M2_PCIE_TX2N Output
H22 PIN_TXP_RC1_2 D85_M2_PCIE_TX2P Output
J24 PIN_RXN_RC1_3 D85_M2_PCIE_RX3N Input
J25 PIN_RXP_RC1_3 D85_M2_PCIE_RX3P Input
K21 PIN_TXN_RC1_3 D85_M2_PCIE_TX3N Output
K22 PIN_TXP_RC1_3 D85_M2_PCIE_TX3P Output
L24 PIN_RXN_EP_0 D85_SOC_PCIE_TX3P Input
L25 PIN_RXP_EP_0 D85_SOC_PCIE_TX3N Input
M8 PIN_CAL_NF S50_/NAND_WP Output
M21 PIN_TXN_EP_0 D85_SOC_PCIE_RX3P Output
M22 PIN_TXP_EP_0 D85_SOC_PCIE_RX3N Output
N8 PIN_VREF_NF[0] 1.2V_FC_VDDQFIO Input
N24 PIN_RXN_EP_1 D85_SOC_PCIE_TX2P Input
N25 PIN_RXP_EP_1 D85_SOC_PCIE_TX2N Input
P21 PIN_TXN_EP_1 D85_SOC_PCIE_RX2P Output
P22 PIN_TXP_EP_1 D85_SOC_PCIE_RX2N Output
R24 PIN_RXN_EP_2 D85_SOC_PCIE_TX1P Input
R25 PIN_RXP_EP_2 D85_SOC_PCIE_TX1N Input
T17 PIN_ISET GND Input Ground
T19 PIN_PERSTN PCIE_PERSTN Output
T21 PIN_TXN_EP_2 D85_SOC_PCIE_RX1P Output
T22 PIN_TXP_EP_2 D85_SOC_PCIE_RX1N Output
U19 PIN_JT0_CLK Not connected
U24 PIN_RXN_EP_3 D85_SOC_PCIE_TX0P Input
U25 PIN_RXP_EP_3 D85_SOC_PCIE_TX0N Input
V1 PIN_RE_CH1 D90_NAND_CH1_RE_ P Output
V2 PIN_REB_CH1 D90_NAND_CH1_RE_ N S50_/ Output
V3 PIN_CE1_CH1 S50_/NAND_CH2_CE1 Output
V4 PIN_CE0_CH1 S50_/NAND_CH2_CE0 Output
V5 PIN_ALE_CH1 S50_NAND_CH1_ALE Output
V6 PIN_CLE_CH1 S50_NAND_CH1_CLE Output
V18 PIN_TEST[0] Not connected
V13 PIN_TEST[13] Not connected
V14 PIN_TEST[8] Not connected
V15 PIN_TEST[5] Not connected
V16 PIN_TEST[7] Not connected
V19 PIN_JT0_TMS Not connected
V21 PIN_TXN_EP_3 D85_SOC_PCIE_RX0P Output
V22 PIN_TXP_EP_3 D85_SOC_PCIE_RX0N Output
W1 PIN_AD_CH1[7] S50_NAND_CH1_AD7 Others
W2 PIN_AD_CH1[6] S50_NAND_CH1_AD6 Others
W4 PIN_AD_CH1[5] S50_NAND_CH1_AD5 Others
W5 PIN_WE_CH1 NAND_CH1_WE Output
W6 PIN_CE2_CH1 Not connected
W7 PIN_CE3_CH1 Not connected
W12 PIN_TEST[15] Not connected
W13 PIN_TEST[9] Not connected
W14 PIN_TEST[3] Not connected
W16 PIN_TEST[12] Not connected
W17 PIN_TEST[6] Not connected
W18 PIN_TEST[1] Not connected
W19 PIN_CTS GND Input Ground
W20 PIN_RTS Not connected
W24 PIN_RXN_RC0 D85_FC_RX0N Input
W25 PIN_RXP_RC0 D85_FC_RX0P Input
Y1 PIN_DQSB_CH1 D90_NAND_CH1_DQS_ P Others
Y2 PIN_DQS_CH1 D90_NAND_CH1_DQS_ N Others
Y3 PIN_AD_CH1[4] S50_NAND_CH1_AD4 Others
Y4 PIN_AD_CH1[3] S50_NAND_CH1_AD3 Others
Y5 PIN_AD_CH1[2] S50_NAND_CH1_AD2 Others
Y7 PIN_WP S50_/NAND_WP Output
Y13 PIN_TEST[16] Not connected
Y14 PIN_TEST[11] Not connected
Y15 PIN_TEST[10] Not connected
Y16 PIN_TEST[14] Not connected
Y17 PIN_TEST[4] Not connected
Y19 PIN_GPIO_0 FC_MANU_MODE_SEL Others
Y21 PIN_TXN_RC0 D85_FC_TX0N Output
Y18 PIN_TEST[2] Not connected
Y22 PIN_TXP_RC0 D85_FC_TX0P Output

Pictures

CXD90062GG.jpeg
CXD90062GG2.jpeg
50980106477 3117f2d5c0 o.jpg CXD90062GG Proto.png

Sources

https://www.flickr.com/photos/130561288@N04/albums/72157718290760702

Retrieved from "http://www.psdevwiki.com/ps5/index.php?title=CXD90062GG&oldid=3155"