CXD90062GG: Difference between revisions

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(→‎Pinout: Merge all pinout tables to one table)
(→‎Pinout: Added GPIO&TEST and UART, also reorganize alphabetically.)
Line 12: Line 12:
!Description
!Description
|-
|-
|C24
|AA12
|PIN_RXN_RC1_0
|PIN_VREFSMIO
|D85_M2_PCIE_RX0N
|1.2V_FC_VDDQMIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|C25
|PIN_RXP_RC1_0
|D85_M2_PCIE_RX0P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|
|-
|-
|D21
|AA14
|PIN_TXN_RC1_0
|PIN_GPIO_7
|D85_M2_PCIE_TX0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|
|-
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|D22
|PIN_TXP_RC1_0
|D85_M2_PCIE_TX0P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|E24
|PIN_RXN_RC1_1
|D85_M2_PCIE_RX1N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|E25
|PIN_RXP_RC1_1
|D85_M2_PCIE_RX1P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|F21
|PIN_TXN_RC1_1
|D85_M2_PCIE_TX1N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|F22
|PIN_TXP_RC1_1
|D85_M2_PCIE_TX1P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|G24
|PIN_RXN_RC1_2
|D85_M2_PCIE_RX2N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|G25
|PIN_RXP_RC1_2
|D85_M2_PCIE_RX2P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|H21
|PIN_TXN_RC1_2
|D85_M2_PCIE_TX2N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|H22
|PIN_TXP_RC1_2
|D85_M2_PCIE_TX2P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|J24
|PIN_RXN_RC1_3
|D85_M2_PCIE_RX3N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|
|-
|-
|J25
|AA15
|PIN_RXP_RC1_3
|PIN_SOC_V_RST
|D85_M2_PCIE_RX3P
|/FC_RESET
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|
|-
|-
|K21
|AA16
|PIN_TXN_RC1_3
|PIN_GPIO_6
|D85_M2_PCIE_TX3N
|PCIE_PEDET
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|K22
|PIN_TXP_RC1_3
|D85_M2_PCIE_TX3P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|L24
|PIN_RXN_EP_0
|D85_SOC_PCIE_TX3P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|
|-
|-
|L25
|AA17
|PIN_RXP_EP_0
|PIN_GPIO_5
|D85_SOC_PCIE_TX3N
|3.3V_FC_VDDQ_MISC
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|
|-
|-
|M21
|AA18
|PIN_TXN_EP_0
|PIN_GPIO_4
|D85_SOC_PCIE_RX3P
|3.3V_FC_VDDQ_MISC
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|M22
|PIN_TXP_EP_0
|D85_SOC_PCIE_RX3N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|N24
|PIN_RXN_EP_1
|D85_SOC_PCIE_TX2P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|N25
|PIN_RXP_EP_1
|D85_SOC_PCIE_TX2N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|
|-
|-
|P21
|AA19
|PIN_TXN_EP_1
|PIN_GPIO_2
|D85_SOC_PCIE_RX2P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|P22
|PIN_TXP_EP_1
|D85_SOC_PCIE_RX2N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|R24
|PIN_RXN_EP_2
|D85_SOC_PCIE_TX1P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|R25
|PIN_RXP_EP_2
|D85_SOC_PCIE_TX1N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|T19
|PIN_PERSTN
|PCIE_PERSTN
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|T21
|PIN_TXN_EP_2
|D85_SOC_PCIE_RX1P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|T22
|PIN_TXP_EP_2
|D85_SOC_PCIE_RX1N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|U19
|PIN_JT0_CLK
|
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|U24
|PIN_RXN_EP_3
|D85_SOC_PCIE_TX0P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|U25
|PIN_RXP_EP_3
|D85_SOC_PCIE_TX0N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|V19
|PIN_JT0_TMS
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|V21
|PIN_TXN_EP_3
|D85_SOC_PCIE_RX0P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V22
|PIN_TXP_EP_3
|D85_SOC_PCIE_RX0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|W24
|PIN_RXN_RC0
|D85_FC_RX0N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|W25
|PIN_RXP_RC0
|D85_FC_RX0P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|Y21
|PIN_TXN_RC0
|D85_FC_TX0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|Y22
|PIN_TXP_RC0
|D85_FC_TX0P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AA12
|PIN_VREFSMIO
|1.2V_FC_VDDQMIO
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|
|-
|-
Line 346: Line 148:
|S50_FC_DDR_DM
|S50_FC_DDR_DM
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AB20
|PIN_GPIO_1
|FC_BOOT_CPU_SEL
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|
|-
|-
Line 406: Line 214:
|S50_FC_DDR_D0
|S50_FC_DDR_D0
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AC20
|PIN_GPIO_3
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|
|-
|-
Line 418: Line 232:
|
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AC24
|PIN_XTLOUT
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|AC25
|PIN_XTLIN
|S50G_FC_SYSCLK
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|
|-
|-
Line 490: Line 316:
|D90_FC_DDR_DQS0_P
|D90_FC_DDR_DQS0_P
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AD20
|PIN_RX2
|FC_UART2_RX
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|AD21
|PIN_TX
|FC_UART1_TX
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|
|-
|-
Line 580: Line 418:
|D90_FC_DDR_DQS0_N
|D90_FC_DDR_DQS0_N
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|AE20
|PIN_TX2
|FC_UART2_TX
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|AE21
|PIN_RX
|FC_UART1_RX
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|
|-
|-
Line 592: Line 442:
|
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|C24
|PIN_RXN_RC1_0
|D85_M2_PCIE_RX0N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|C25
|PIN_RXP_RC1_0
|D85_M2_PCIE_RX0P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|D21
|PIN_TXN_RC1_0
|D85_M2_PCIE_TX0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|D22
|PIN_TXP_RC1_0
|D85_M2_PCIE_TX0P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|E24
|PIN_RXN_RC1_1
|D85_M2_PCIE_RX1N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|E25
|PIN_RXP_RC1_1
|D85_M2_PCIE_RX1P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|F21
|PIN_TXN_RC1_1
|D85_M2_PCIE_TX1N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|F22
|PIN_TXP_RC1_1
|D85_M2_PCIE_TX1P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|G24
|PIN_RXN_RC1_2
|D85_M2_PCIE_RX2N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|G25
|PIN_RXP_RC1_2
|D85_M2_PCIE_RX2P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|H21
|PIN_TXN_RC1_2
|D85_M2_PCIE_TX2N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|H22
|PIN_TXP_RC1_2
|D85_M2_PCIE_TX2P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|J24
|PIN_RXN_RC1_3
|D85_M2_PCIE_RX3N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|J25
|PIN_RXP_RC1_3
|D85_M2_PCIE_RX3P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|K21
|PIN_TXN_RC1_3
|D85_M2_PCIE_TX3N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|K22
|PIN_TXP_RC1_3
|D85_M2_PCIE_TX3P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|L24
|PIN_RXN_EP_0
|D85_SOC_PCIE_TX3P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|L25
|PIN_RXP_EP_0
|D85_SOC_PCIE_TX3N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|M21
|PIN_TXN_EP_0
|D85_SOC_PCIE_RX3P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|M22
|PIN_TXP_EP_0
|D85_SOC_PCIE_RX3N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|N24
|PIN_RXN_EP_1
|D85_SOC_PCIE_TX2P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|N25
|PIN_RXP_EP_1
|D85_SOC_PCIE_TX2N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|P21
|PIN_TXN_EP_1
|D85_SOC_PCIE_RX2P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|P22
|PIN_TXP_EP_1
|D85_SOC_PCIE_RX2N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|R24
|PIN_RXN_EP_2
|D85_SOC_PCIE_TX1P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|R25
|PIN_RXP_EP_2
|D85_SOC_PCIE_TX1N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|T17
|PIN_ISET
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|T19
|PIN_PERSTN
|PCIE_PERSTN
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|T21
|PIN_TXN_EP_2
|D85_SOC_PCIE_RX1P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|T22
|PIN_TXP_EP_2
|D85_SOC_PCIE_RX1N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|U19
|PIN_JT0_CLK
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|U24
|PIN_RXN_EP_3
|D85_SOC_PCIE_TX0P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|U25
|PIN_RXP_EP_3
|D85_SOC_PCIE_TX0N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|V18
|PIN_TEST[0]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|V13
|PIN_TEST[13]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|V14
|PIN_TEST[8]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|V15
|PIN_TEST[5]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|V16
|PIN_TEST[7]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|V19
|PIN_JT0_TMS
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|V21
|PIN_TXN_EP_3
|D85_SOC_PCIE_RX0P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|V22
|PIN_TXP_EP_3
|D85_SOC_PCIE_RX0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|W12
|PIN_TEST[15]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W13
|PIN_TEST[9]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W14
|PIN_TEST[3]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W16
|PIN_TEST[12]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W17
|PIN_TEST[6]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W18
|PIN_TEST[1]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W19
|PIN_CTS
|GND
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|Ground
|-
|W20
|PIN_RTS
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|W24
|PIN_RXN_RC0
|D85_FC_RX0N
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|W25
|PIN_RXP_RC0
|D85_FC_RX0P
|[[File:IC-Pin-in.png|alt=Input|frameless]]
|
|-
|Y13
|PIN_TEST[16]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|Y14
|PIN_TEST[11]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|Y15
|PIN_TEST[10]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|Y16
|PIN_TEST[14]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|Y17
|PIN_TEST[4]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|Y19
|PIN_GPIO_0
|FC_MANU_MODE_SEL
|[[File:IC-Pin-Out.png|alt=Others|frameless]]
|
|-
|Y21
|PIN_TXN_RC0
|D85_FC_TX0N
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|-
|Y18
|PIN_TEST[2]
|
|[[File:Pin-nc.png|alt=Not connected|frameless]]
|
|-
|Y22
|PIN_TXP_RC0
|D85_FC_TX0P
|[[File:Pin out.png|alt=Output|frameless|24x24px]]
|
|
|-
|-

Revision as of 19:28, 12 December 2024

NVME Controller


Pinout

Pad Internal Name External Name Type Description
AA12 PIN_VREFSMIO 1.2V_FC_VDDQMIO Input
AA14 PIN_GPIO_7 Not connected
AA15 PIN_SOC_V_RST /FC_RESET Input
AA16 PIN_GPIO_6 PCIE_PEDET Input
AA17 PIN_GPIO_5 3.3V_FC_VDDQ_MISC Input
AA18 PIN_GPIO_4 3.3V_FC_VDDQ_MISC Input
AA19 PIN_GPIO_2 Not connected
AA20 PIN_F_CS_N /FC_SPI_CS Input
AA24 PIN_REFCLK_P_0 D100G_FC_PCIE_CLK_P Input
AA25 PIN_REFCLK_N_0 D100G_FC_PCIE_CLK_N Input
AB7 PIN_M_A[15] S50_FC_DDR_A15 Output
AB8 PIN_M_A[11] S50_FC_DDR_A11 Output
AB9 PIN_M_A[8] S50_FC_DDR_A8 Output
AB10 PIN_M_A[4] S50_FC_DDR_A4 Output
AB11 PIN_M_ALERT_N S50_/FC_DDR_ALERTN Output
AB12 PIN_DDR_CAL GND Input Ground
AB13 PIN_M_ODT[0] S50_FC_DDR_ODT0 Output
AB14 PIN_M_CS_N[0] S50_FC_DDR_CS0N Output
AB15 PIN_M_D[7] S50_FC_DDR_D7 Others
AB16 PIN_M_D[6] S50_FC_DDR_D6 Others
AB17 PIN_M_D[2] S50_FC_DDR_D2 Others
AB18 PIN_M_D[1] S50_FC_DDR_D1 Others
AB19 PIN_M_DM S50_FC_DDR_DM Output
AB20 PIN_GPIO_1 FC_BOOT_CPU_SEL Others
AB21 PIN_F_Q SSB_SPIM_MISO Output
AB22 PIN_JT0_DI Not connected
AC7 PIN_M_A[14] S50_FC_DDR_A14 Output
AC9 PIN_M_A[7] S50_FC_DDR_A7 Output
AC10 PIN_M_A[3] S50_FC_DDR_A3 Output
AC12 PIN_M_PAR S50_FC_DDR_PAR Output
AC14 PIN_M_CS_N[1] N/C Not connected No Connection
AC15 PIN_M_WE_N S50_FC_DDR_WEN Output
AC17 PIN_M_D[3] S50_FC_DDR_D3 Others
AC19 PIN_M_D[0] S50_FC_DDR_D0 Others
AC20 PIN_GPIO_3 Not connected
AC21 PIN_F_SPI_INT /FC_SPI_S_INT Output
AC22 PIN_JT0_TRSTN Not connected
AC24 PIN_XTLOUT Not connected
AC25 PIN_XTLIN S50G_FC_SYSCLK Input
AD7 PIN_M_A[13] S50_FC_DDR_A13 Output
AD8 PIN_M_A[9] S50_FC_DDR_A9 Output
AD9 PIN_M_A[6] S50_FC_DDR_A6 Output
AD10 PIN_M_A[2] S50_FC_DDR_A2 Output
AD11 PIN_M_BA[2] S50_FC_DDR_BA2 Output
AD12 PIN_M_BA[0] S50_FC_DDR_BA0 Output
AD13 PIN_M_ODT[1] N/C Not connected No Connection
AD14 PIN_M_CKE[0] S50_FC_DDR_CKE0 Output
AD15 PIN_M_CAS_N S50_/FC_DDR_CASN Output
AD16 PIN_M_CLOCK[0] D90_FC_DDR_CLOCK0_P Output
AD17 PIN_M_D[4] S50_FC_DDR_D4 Others
AD18 PIN_M_DQS_P[0] D90_FC_DDR_DQS0_P Others
AD20 PIN_RX2 FC_UART2_RX Input
AD21 PIN_TX FC_UART1_TX Output
AD22 PIN_F_D SSB_SPIM_MOSI Input
AD23 PIN_CLK_REQ_N_0 /FC_CLK_REQ_N Output
AD24 PIN_ANA_TP Not connected
AE7 PIN_M_A[12] S50_FC_DDR_A12 Output
AE8 PIN_M_A[10] S50_FC_DDR_A10 Output
AE9 PIN_M_A[5] S50_FC_DDR_A5 Output
AE10 PIN_M_A[1] S50_FC_DDR_A1 Output
AE11 PIN_M_A[0] S50_FC_DDR_A0 Output
AE12 PIN_M_BA[1] S50_FC_DDR_BA1 Output
AE13 PIN_M_RST_N NS50_/FC_DDR_RSTN Output
AE14 PIN_M_CKE[1] GND Input Ground
AE15 PIN_M_RAS_N S50_/FC_DDR_RASN Output
AE16 PIN_M_CLOCK_N[0] D90_FC_DDR_CLOCK0_N Output
AE17 PIN_M_D[5] S50_FC_DDR_D5 Others
AE18 PIN_M_DQS_N[0] D90_FC_DDR_DQS0_N Others
AE20 PIN_TX2 FC_UART2_TX Output
AE21 PIN_RX FC_UART1_RX Input
AE22 PIN_F_CLK SSB_SPIM_CLK Input
AE23 PIN_JT0_DO Not connected
C24 PIN_RXN_RC1_0 D85_M2_PCIE_RX0N Input
C25 PIN_RXP_RC1_0 D85_M2_PCIE_RX0P Input
D21 PIN_TXN_RC1_0 D85_M2_PCIE_TX0N Output
D22 PIN_TXP_RC1_0 D85_M2_PCIE_TX0P Output
E24 PIN_RXN_RC1_1 D85_M2_PCIE_RX1N Input
E25 PIN_RXP_RC1_1 D85_M2_PCIE_RX1P Input
F21 PIN_TXN_RC1_1 D85_M2_PCIE_TX1N Output
F22 PIN_TXP_RC1_1 D85_M2_PCIE_TX1P Output
G24 PIN_RXN_RC1_2 D85_M2_PCIE_RX2N Input
G25 PIN_RXP_RC1_2 D85_M2_PCIE_RX2P Input
H21 PIN_TXN_RC1_2 D85_M2_PCIE_TX2N Output
H22 PIN_TXP_RC1_2 D85_M2_PCIE_TX2P Output
J24 PIN_RXN_RC1_3 D85_M2_PCIE_RX3N Input
J25 PIN_RXP_RC1_3 D85_M2_PCIE_RX3P Input
K21 PIN_TXN_RC1_3 D85_M2_PCIE_TX3N Output
K22 PIN_TXP_RC1_3 D85_M2_PCIE_TX3P Output
L24 PIN_RXN_EP_0 D85_SOC_PCIE_TX3P Input
L25 PIN_RXP_EP_0 D85_SOC_PCIE_TX3N Input
M21 PIN_TXN_EP_0 D85_SOC_PCIE_RX3P Output
M22 PIN_TXP_EP_0 D85_SOC_PCIE_RX3N Output
N24 PIN_RXN_EP_1 D85_SOC_PCIE_TX2P Input
N25 PIN_RXP_EP_1 D85_SOC_PCIE_TX2N Input
P21 PIN_TXN_EP_1 D85_SOC_PCIE_RX2P Output
P22 PIN_TXP_EP_1 D85_SOC_PCIE_RX2N Output
R24 PIN_RXN_EP_2 D85_SOC_PCIE_TX1P Input
R25 PIN_RXP_EP_2 D85_SOC_PCIE_TX1N Input
T17 PIN_ISET GND Input Ground
T19 PIN_PERSTN PCIE_PERSTN Output
T21 PIN_TXN_EP_2 D85_SOC_PCIE_RX1P Output
T22 PIN_TXP_EP_2 D85_SOC_PCIE_RX1N Output
U19 PIN_JT0_CLK Not connected
U24 PIN_RXN_EP_3 D85_SOC_PCIE_TX0P Input
U25 PIN_RXP_EP_3 D85_SOC_PCIE_TX0N Input
V18 PIN_TEST[0] Not connected
V13 PIN_TEST[13] Not connected
V14 PIN_TEST[8] Not connected
V15 PIN_TEST[5] Not connected
V16 PIN_TEST[7] Not connected
V19 PIN_JT0_TMS Not connected
V21 PIN_TXN_EP_3 D85_SOC_PCIE_RX0P Output
V22 PIN_TXP_EP_3 D85_SOC_PCIE_RX0N Output
W12 PIN_TEST[15] Not connected
W13 PIN_TEST[9] Not connected
W14 PIN_TEST[3] Not connected
W16 PIN_TEST[12] Not connected
W17 PIN_TEST[6] Not connected
W18 PIN_TEST[1] Not connected
W19 PIN_CTS GND Input Ground
W20 PIN_RTS Not connected
W24 PIN_RXN_RC0 D85_FC_RX0N Input
W25 PIN_RXP_RC0 D85_FC_RX0P Input
Y13 PIN_TEST[16] Not connected
Y14 PIN_TEST[11] Not connected
Y15 PIN_TEST[10] Not connected
Y16 PIN_TEST[14] Not connected
Y17 PIN_TEST[4] Not connected
Y19 PIN_GPIO_0 FC_MANU_MODE_SEL Others
Y21 PIN_TXN_RC0 D85_FC_TX0N Output
Y18 PIN_TEST[2] Not connected
Y22 PIN_TXP_RC0 D85_FC_TX0P Output

Pictures

CXD90062GG.jpeg
CXD90062GG2.jpeg
50980106477 3117f2d5c0 o.jpg CXD90062GG Proto.png

Sources

https://www.flickr.com/photos/130561288@N04/albums/72157718290760702

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