CXD90062GG: Difference between revisions
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NVME Controller | NVME Controller | ||
== Pinout == | == Pinout == | ||
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= Pictures = | |||
[[File:CXD90062GG.jpeg]]<br> | |||
[[File:CXD90062GG2.jpeg]]<br> | |||
[[File:50980106477 3117f2d5c0 o.jpg|500px]] | |||
[[File:CXD90062GG_Proto.png]] | |||
== Sources == | == Sources == | ||
https://www.flickr.com/photos/130561288@N04/albums/72157718290760702 | https://www.flickr.com/photos/130561288@N04/albums/72157718290760702 | ||
Revision as of 23:14, 11 December 2024
NVME Controller
Pinout
DDR4
| Pad | Internal Name | External Name | Type | Description |
|---|---|---|---|---|
| AA12 | PIN_VREFSMIO | 1.2V_FC_VDDQMIO | 
|
|
| AB7 | PIN_M_A[15] | S50_FC_DDR_A15 | 
|
|
| AB8 | PIN_M_A[11] | S50_FC_DDR_A11 |
|
|
| AB9 | PIN_M_A[8] | S50_FC_DDR_A8 |
|
|
| AB10 | PIN_M_A[4] | S50_FC_DDR_A4 |
|
|
| AB11 | PIN_M_ALERT_N | S50_/FC_DDR_ALERTN |
|
|
| AB12 | PIN_DDR_CAL | GND |
|
Ground |
| AB13 | PIN_M_ODT[0] | S50_FC_DDR_ODT0 |
|
|
| AB14 | PIN_M_CS_N[0] | S50_FC_DDR_CS0N |
|
|
| AB15 | PIN_M_D[7] | S50_FC_DDR_D7 | 
|
|
| AB16 | PIN_M_D[6] | S50_FC_DDR_D6 |
|
|
| AB17 | PIN_M_D[2] | S50_FC_DDR_D2 |
|
|
| AB18 | PIN_M_D[1] | S50_FC_DDR_D1 |
|
|
| AB19 | PIN_M_DM | S50_FC_DDR_DM |
|
|
| AC7 | PIN_M_A[14] | S50_FC_DDR_A14 |
|
|
| AC9 | PIN_M_A[7] | S50_FC_DDR_A7 |
|
|
| AC10 | PIN_M_A[3] | S50_FC_DDR_A3 |
|
|
| AC12 | PIN_M_PAR | S50_FC_DDR_PAR |
|
|
| AC14 | PIN_M_CS_N[1] | N/C | 
|
No Connection |
| AC15 | PIN_M_WE_N | S50_FC_DDR_WEN |
|
|
| AC17 | PIN_M_D[3] | S50_FC_DDR_D3 |
|
|
| AC19 | PIN_M_D[0] | S50_FC_DDR_D0 |
|
|
| AD7 | PIN_M_A[13] | S50_FC_DDR_A13 |
|
|
| AD8 | PIN_M_A[9] | S50_FC_DDR_A9 |
|
|
| AD9 | PIN_M_A[6] | S50_FC_DDR_A6 |
|
|
| AD10 | PIN_M_A[2] | S50_FC_DDR_A2 |
|
|
| AD11 | PIN_M_BA[2] | S50_FC_DDR_BA2 |
|
|
| AD12 | PIN_M_BA[0] | S50_FC_DDR_BA0 |
|
|
| AD13 | PIN_M_ODT[1] | N/C |
|
No Connection |
| AD14 | PIN_M_CKE[0] | S50_FC_DDR_CKE0 |
|
|
| AD15 | PIN_M_CAS_N | S50_/FC_DDR_CASN |
|
|
| AD16 | PIN_M_CLOCK[0] | D90_FC_DDR_CLOCK0_P |
|
|
| AD17 | PIN_M_D[4] | S50_FC_DDR_D4 |
|
|
| AD18 | PIN_M_DQS_P[0] | D90_FC_DDR_DQS0_P |
|
|
| AE7 | PIN_M_A[12] | S50_FC_DDR_A12 |
|
|
| AE8 | PIN_M_A[10] | S50_FC_DDR_A10 |
|
|
| AE9 | PIN_M_A[5] | S50_FC_DDR_A5 |
|
|
| AE10 | PIN_M_A[1] | S50_FC_DDR_A1 |
|
|
| AE11 | PIN_M_A[0] | S50_FC_DDR_A0 |
|
|
| AE12 | PIN_M_BA[1] | S50_FC_DDR_BA1 |
|
|
| AE13 | PIN_M_RST_N | NS50_/FC_DDR_RSTN |
|
|
| AE14 | PIN_M_CKE[1] | GND |
|
Ground |
| AE15 | PIN_M_RAS_N | S50_/FC_DDR_RASN |
|
|
| AE16 | PIN_M_CLOCK_N[0] | D90_FC_DDR_CLOCK0_N |
|
|
| AE17 | PIN_M_D[5] | S50_FC_DDR_D5 |
|
|
| AE18 | PIN_M_DQS_N[0] | D90_FC_DDR_DQS0_N |
|
Pictures
Sources
https://www.flickr.com/photos/130561288@N04/albums/72157718290760702