K4A4G085WF-BCTD

From PS5 Developer wiki
Revision as of 20:15, 13 December 2024 by Labelior (talk | contribs) (→‎Pinout: Added K4A4G085WF-BCTD)
Jump to navigation Jump to search

Pinout

Pad Internal Name External Name Type Description
A1 VDD_A1 1.2V_FC_VDDQMIO Input
A2 VSSQ_A2 GND Input Ground
A3 TDQS_c Not connected
A7 DM/DBI/TDQS_t S50_FC_DDR_DM Input
A8 VSSQ_A8 GND Input Ground
A9 VSS_A9 GND Input Ground
B1 BPP_B1 2.5V_DDR4_VPP Input
B2 VDDQ_B2 1.2V_FC_VDDQMIO Input
B3 DQS_c D90_FC_DDR_DQS0_N Others
B7 DQ1 S50_FC_DDR_D0 Others
B8 VDDQ_B8 1.2V_FC_VDDQMIO Input
B9 ZQ GND Input Ground
C1 VDDQ_C1 1.2V_FC_VDDQMIO Input
C2 DQ0 S50_FC_DDR_D3 Others
C3 DQS_t D90_FC_DDR_DQS0_P Others
C7 VDD_C7 1.2V_FC_VDDQMIO Input
C8 VSS_C8 GND Input Ground
C9 VDDQ_C9 1.2V_FC_VDDQMIO Input
D1 VSSQ_D1 GND Input Ground
D2 DQ4 S50_FC_DDR_D4 Others
D3 DQ2 S50_FC_DDR_D5 Others
D7 DQ3 S50_FC_DDR_D2 Others
D8 DQ5 S50_FC_DDR_D1 Others
D9 VSSQ_D9 GND Input Ground
E1 VSS_E1 GND Input Ground
E2 VDDQ_E2 1.2V_FC_VDDQMIO Input
E3 DQ6 S50_FC_DDR_D6 Others
E7 DQ7 S50_FC_DDR_D7 Others
E8 VDDQ_E8 1.2V_FC_VDDQMIO Input
E9 VSS_E9 GND Input Ground
F1 VDD_F1 1.2V_FC_VDDQMIO Input
F2 NC_F2 Not connected
F3 ODT S50_FC_DDR_ODT0 Input
F7 CK_t D90_FC_DDR_CLOCK0_P Input
F8 CK_c D90_FC_DDR_CLOCK0_N Input
F9 VDD_F9 1.2V_FC_VDDQMIO Input
G1 VSS_G1 GND Input Ground
G2 NC_G2 Not connected
G3 CKE S50_FC_DDR_CKE0 Input
G7 \CS S50_FC_DDR_CS0N Input
G8 NC_G8 Not connected
G9 NC_G9 GND Input Ground
H1 VDD_H1 1.2V_FC_VDDQMIO Input
H2 \WE/A14 S50_FC_DDR_WEN Input
H3 \ACT S50_FC_DDR_A14 Input
H7 \CAS S50_/FC_DDR_CASN Input
H8 \RAS S50_/FC_DDR_RASN Input
H9 VSS_G9 GND Input Ground
J1 VREFCA 1.2V_FC_VDDQMIO Input
J2 BG0 S50_FC_DDR_BA2 Input
J3 A10/AP S50_FC_DDR_A10 Input
J7 A12/\BC S50_FC_DDR_A12 Input
J8 BG1 S50_FC_DDR_A15 Input
J9 VDD_J9 1.2V_FC_VDDQMIO Input
K1 VSS_K1 GND Input Ground
K2 BA0 S50_FC_DDR_BA0 Input
K3 A4 S50_FC_DDR_A4 Input
K7 A3 S50_FC_DDR_A3 Input
K8 BA1 S50_FC_DDR_BA1 Input
K9 VSS_K9 GND Input Ground
L1 \RESET S50_/FC_DDR_RSTN Input
L2 A6 S50_FC_DDR_A6 Input
L3 A0 S50_FC_DDR_A0 Input
L7 A1 S50_FC_DDR_A1 Input
L8 A5 S50_FC_DDR_A5 Input
L9 \ALERT S50_/FC_DDR_ALERTN Input
M1 VDD_M1 1.2V_FC_VDDQMIO Input
M2 A8 S50_FC_DDR_A8 Input
M3 A2 S50_FC_DDR_A2 Input
M7 A9 S50_FC_DDR_A9 Input
M8 A7 S50_FC_DDR_A7 Input
M9 VPP_M9 2.5V_DDR4_VPP Input
N1 VSS_N1 GND Input Ground
N2 A11 S50_FC_DDR_A11 Input
N3 PAR S50_FC_DDR_PAR Input
N7 NC_N7 Not connected
N8 A13 S50_FC_DDR_A13 Input
N9 VDD_N9 1.2V_FC_VDDQMIO Input

Pictures

K4A4G085WF-BCTD.png K4A4G085WF-BCTD Proto.png