Editing Codenames
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* Sycorax (CP Box KBL, The Tempest) | * Sycorax (CP Box KBL, The Tempest) | ||
* Setebos (CP Box EMC Firmware, The Tempest) | * Setebos (CP Box EMC Firmware, The Tempest) | ||
* Oberon (CPU Part of | * Oberon (CPU Part of APU, Dream of a Summer Night) | ||
* Viola (CPU Part of Pro APU, Twelfth Night) | |||
* Viola (CPU Part of | |||
* Titania (EFC/EAP, Dream of a Summer Night). Titania has its own Power Management Integrated Circuit and GPIO proving it is a microcontroller. It has access to PCIe hence why it was suspected to be the PS5 internal SSD controller. | * Titania (EFC/EAP, Dream of a Summer Night). Titania has its own Power Management Integrated Circuit and GPIO proving it is a microcontroller. It has access to PCIe hence why it was suspected to be the PS5 internal SSD controller. | ||
* Ariel (GPU Part of APU, The Tempest) | * Ariel (GPU Part of APU, The Tempest) | ||
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= Island Codenames = | = Island Codenames = | ||
* Salina (First revision of PS5 Southbridge) -> according to shuffle from fail0verflow, Salina is | * Salina (First revision of PS5 Southbridge) -> according to shuffle from fail0verflow, Salina is EMC (to debunk). Titania has its own Power Management Integrated Circuit. Salina is related to DSP0 (Digital Sound Processor 0) and EP (?). | ||
* Sierra (Second revision of PS5 Southbridge) | * Sierra (Second revision of PS5 Southbridge) | ||
* Tahoe (First revision of PS5 Southbridge) | * Tahoe (First revision of PS5 Southbridge) | ||