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[[File:CXD90061GG.png|thumb|SIE CXD90061GG]]
EMC/EAP Chip (with SysCon bundled?)
EMC/EAP Chip (with SysCon bundled?)


* Credit to dan2wik for the third , fourth and fifth picture
* Credit to dan2wik for the third , fourth and fifth picture
* Mediatek 3613 Chip
* Mediatek 3613 Chip
* Codename Salina


= Pinout =
= Pinout =
Line 62: Line 60:
|1.15V_SS_PG3_SATA1
|1.15V_SS_PG3_SATA1
|
|
|Sata1 PHY supply
|
|-
|-
|A10
|A10
Line 74: Line 72:
|3.3V_SS_SATA_PG3
|3.3V_SS_SATA_PG3
|
|
|Sata1 Core supply
|
|-
|-
|A13
|A13
Line 80: Line 78:
|D90_SSB_USB2_DPLS
|D90_SSB_USB2_DPLS
|
|
|USB 2.0 Port2 D+
|
|-
|-
|A15
|A15
Line 86: Line 84:
|/FC_CLK_REQ_N
|/FC_CLK_REQ_N
|
|
|Flash Controller clock request
|
|-
|-
|A16
|A16
Line 116: Line 114:
|3.3V_SS_PG1_XTAL
|3.3V_SS_PG1_XTAL
|
|
|Supply for PLL for EMC
|
|-
|-
|B3
|B3
Line 176: Line 174:
|D90_SSB_USB2_DMNS
|D90_SSB_USB2_DMNS
|
|
|USB 2.0 Port2 D-
|
|-
|-
|B14
|B14
Line 182: Line 180:
|N/C (?)
|N/C (?)
|
|
|Test point only (?) USB Port2 overcurrent det.
|Test point only (?)
|-
|-
|B15
|B15
Line 188: Line 186:
|/SSB_WIFI_CLKREQ
|/SSB_WIFI_CLKREQ
|
|
|Wifi PCI-e clock request
|
|-
|-
|B16
|B16
Line 200: Line 198:
|SSB_GPI
|SSB_GPI
|
|
|Interrupt for optional external ethernet PHY
|
|-
|-
|B18
|B18
Line 224: Line 222:
|1.8V_SS_PG1_CLK
|1.8V_SS_PG1_CLK
|
|
|Supply for 27MHz clock gen for Flava
|
|-
|-
|C4
|C4
Line 290: Line 288:
|SSB_USB2_POWEREN
|SSB_USB2_POWEREN
|
|
|USB Port 2 power enable signal
|
|-
|-
|C15
|C15
Line 302: Line 300:
|PSW_PDC
|PSW_PDC
|
|
|USB C PD controller power enable signal (remapped)
|
|-
|-
|C17
|C17
Line 308: Line 306:
|/HDMI_RESET
|/HDMI_RESET
|
|
|Flava reset signal
|
|-
|-
|C18
|C18
|GPIOC_1
|GPIOC_1
|CL5127
|PSW_MSOC_PGA2
|
|
|
|Test pad only.
|-
|-
|D1
|D1
Line 329: Line 327:
|-
|-
|D3
|D3
|CK27M_HDMI
|AVDD33_XTAL
|S50G_HDMI_SYSCLK
|3.3V_SS_PG1_XTAL
|
|
|
|27MHz clock for Flava
|-
|-
|D4
|D4
Line 350: Line 348:
|NC (?)
|NC (?)
|
|
|Test point only (?)  
|Test point only (?)
|-
|-
|D7
|D7
Line 392: Line 390:
|3.3V_SS_SUSB_PG3
|3.3V_SS_SUSB_PG3
|
|
|Supply for the USB Port 2 PHY and core
|
|-
|-
|D14
|D14
Line 422: Line 420:
|THERMISTOR_3
|THERMISTOR_3
|[[File:IC-Pin-in.png|frameless]]
|[[File:IC-Pin-in.png|frameless]]
|Signal for Thermistor located near SSD PMIC
|
|-
|-
|E1
|E1
Line 428: Line 426:
|3.3V_SS_PG1_XTAL
|3.3V_SS_PG1_XTAL
|
|
|Supply for 25MHz oscillator driver
|
|-
|-
|E2
|E2
Line 434: Line 432:
|3.3V_SS_PG2
|3.3V_SS_PG2
|
|
|Supply for the General purpose PLL cluster
|
|-
|-
|E3
|E3
Line 500: Line 498:
|THERMISTOR_1
|THERMISTOR_1
|
|
|Signal for Thermistor located between PSU spike and APU
|
|-
|-
|E17
|E17
Line 506: Line 504:
|THERMISTOR_2
|THERMISTOR_2
|
|
|Signal for Thermistor located on LED Board
|
|-
|-
|F3
|F3
Line 512: Line 510:
|D85_FC_TX0P
|D85_FC_TX0P
|
|
|PCI-e Gen3 RX+ from flash controller.
|
|-
|-
|F4
|F4
Line 518: Line 516:
|D85_FC_TX0N
|D85_FC_TX0N
|
|
|PCI-e Gen3 RX- from flash controller.
|
|-
|-
|F5
|F5
Line 554: Line 552:
|FAN_PWM_1
|FAN_PWM_1
|
|
|Fan speed PWM signal
|
|-
|-
|F14
|F14
Line 578: Line 576:
|GND
|GND
|[[File:IC-Pin-in.png|frameless]]
|[[File:IC-Pin-in.png|frameless]]
|ADC Ground reference
|Ground
|-
|-
|F18
|F18
Line 584: Line 582:
|3.3V_SS_PG1_XTAL
|3.3V_SS_PG1_XTAL
|
|
|ADC Supply reference
|
|-
|-
|G1
|G1
Line 590: Line 588:
|D85_FC_RX0P
|D85_FC_RX0P
|
|
|PCI-e Gen3 TX+ to flash controller.
|
|-
|-
|G2
|G2
Line 596: Line 594:
|D85_FC_RX0N
|D85_FC_RX0N
|
|
|PCI-e Gen3 TX- to flash controller.
|
|-
|-
|G3
|G3
Line 614: Line 612:
|1.15V_SS_PG2
|1.15V_SS_PG2
|
|
|Supply for PCI-e Gen 3 RX PHY
|
|-
|-
|G6
|G6
Line 620: Line 618:
|1.15V_SS_PG2
|1.15V_SS_PG2
|
|
|Supply for PCI-e Gen 3 TX PHY
|
|-
|-
|G7
|G7
Line 656: Line 654:
|BUZZER_PWM
|BUZZER_PWM
|
|
|Buzzer signal output
|
|-
|-
|G13
|G13
Line 668: Line 666:
|D100G_WIFI_PCIE_CLK_P
|D100G_WIFI_PCIE_CLK_P
|
|
|PCI-e Clock+ to wifi with Spread Spectrum Clocking.
|
|-
|-
|G15
|G15
Line 674: Line 672:
|D100G_WIFI_PCIE_CLK_N
|D100G_WIFI_PCIE_CLK_N
|
|
|PCI-e Clock- to wifi with Spread Spectrum Clocking.
|
|-
|-
|G16
|G16
Line 686: Line 684:
|D85_WIFI_RX0P
|D85_WIFI_RX0P
|
|
|PCI-e gen1 RX+ from Wifi module.
|
|-
|-
|G18
|G18
Line 692: Line 690:
|D85_WIFI_RX0N
|D85_WIFI_RX0N
|
|
|PCI-e gen1 RX- from Wifi module.
|
|-
|-
|H3
|H3
Line 698: Line 696:
|D100G_M2_PCIE_CLK_P
|D100G_M2_PCIE_CLK_P
|
|
|PCI-e Clock+ to M.2 slot
|
|-
|-
|H4
|H4
Line 704: Line 702:
|D100G_M2_PCIE_CLK_N
|D100G_M2_PCIE_CLK_N
|
|
|PCI-e Clock- to M.2 slot
|
|-
|-
|H5
|H5
Line 746: Line 744:
|3.3V_SS_PG2
|3.3V_SS_PG2
|
|
|Supply for PCI-e G1 clock PHYs and core
|
|-
|-
|H14
|H14
Line 752: Line 750:
|1.15V_SS_PG2
|1.15V_SS_PG2
|
|
|Supply for PCI-e G1 RX/TX PHYs
|
|-
|-
|H15
|H15
Line 1,310: Line 1,308:
|3.3V_SS_SUSB_PG3
|3.3V_SS_SUSB_PG3
|
|
|Supply for the USB Port 0/1 Core and PHY
|
|-
|-
|P12
|P12
Line 1,759: Line 1,757:
= Pictures =
= Pictures =


[[File:CXD90061GG.png|253x253px]]
[[File:CXD90061GG.png]]
[[File:CXD90061GG_Proto.png|452x452px]]
[[File:CXD90061GG_Proto.png]]
[[File:Image.png|frameless|252x252px]]
[[File:Image.png]]
[[File:Image2.png|254x254px]]
[[File:Image2.png]]
[[File:Image3.png|269x269px]]
[[File:Image3.png]]
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