Editing CXD90061GG

Jump to navigation Jump to search
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then publish the changes below to finish undoing the edit.

Latest revision Your text
Line 1: Line 1:
[[File:CXD90061GG.png|thumb|SIE CXD90061GG]]
EMC/EAP Chip (with SysCon bundled?)
EMC/EAP Chip (with SysCon bundled?)


* Credit to dan2wik for the third , fourth and fifth picture
* Credit to dan2wik for the third , fourth and fifth picture
* Mediatek 3613 Chip
* Codename Salina


= Pinout =
= Pinout =
Line 62: Line 59:
|1.15V_SS_PG3_SATA1
|1.15V_SS_PG3_SATA1
|
|
|Sata1 PHY supply
|
|-
|-
|A10
|A10
Line 74: Line 71:
|3.3V_SS_SATA_PG3
|3.3V_SS_SATA_PG3
|
|
|Sata1 Core supply
|
|-
|-
|A13
|A13
Line 80: Line 77:
|D90_SSB_USB2_DPLS
|D90_SSB_USB2_DPLS
|
|
|USB 2.0 Port2 D+
|
|-
|-
|A15
|A15
Line 86: Line 83:
|/FC_CLK_REQ_N
|/FC_CLK_REQ_N
|
|
|Flash Controller clock request
|
|-
|-
|A16
|A16
Line 116: Line 113:
|3.3V_SS_PG1_XTAL
|3.3V_SS_PG1_XTAL
|
|
|Supply for PLL for EMC
|
|-
|-
|B3
|B3
Line 176: Line 173:
|D90_SSB_USB2_DMNS
|D90_SSB_USB2_DMNS
|
|
|USB 2.0 Port2 D-
|
|-
|-
|B14
|B14
Line 182: Line 179:
|N/C (?)
|N/C (?)
|
|
|Test point only (?) USB Port2 overcurrent det.
|Test point only (?)
|-
|-
|B15
|B15
Line 188: Line 185:
|/SSB_WIFI_CLKREQ
|/SSB_WIFI_CLKREQ
|
|
|Wifi PCI-e clock request
|
|-
|-
|B16
|B16
Line 200: Line 197:
|SSB_GPI
|SSB_GPI
|
|
|Interrupt for optional external ethernet PHY
|
|-
|-
|B18
|B18
Line 224: Line 221:
|1.8V_SS_PG1_CLK
|1.8V_SS_PG1_CLK
|
|
|Supply for 27MHz clock gen for Flava
|
|-
|-
|C4
|C4
Line 290: Line 287:
|SSB_USB2_POWEREN
|SSB_USB2_POWEREN
|
|
|USB Port 2 power enable signal
|
|-
|-
|C15
|C15
Line 302: Line 299:
|PSW_PDC
|PSW_PDC
|
|
|USB C PD controller power enable signal (remapped)
|
|-
|-
|C17
|C17
Line 308: Line 305:
|/HDMI_RESET
|/HDMI_RESET
|
|
|Flava reset signal
|
|-
|-
|C18
|C18
|GPIOC_1
|GPIOC_1
|CL5127
|PSW_MSOC_PGA2
|
|
|
|Test pad only.
|-
|-
|D1
|D1
Line 329: Line 326:
|-
|-
|D3
|D3
|CK27M_HDMI
|AVDD33_XTAL
|S50G_HDMI_SYSCLK
|3.3V_SS_PG1_XTAL
|
|
|
|27MHz clock for Flava
|-
|-
|D4
|D4
Line 350: Line 347:
|NC (?)
|NC (?)
|
|
|Test point only (?)  
|Test point only (?)
|-
|-
|D7
|D7
Line 392: Line 389:
|3.3V_SS_SUSB_PG3
|3.3V_SS_SUSB_PG3
|
|
|Supply for the USB Port 2 PHY and core
|
|-
|-
|D14
|D14
Line 422: Line 419:
|THERMISTOR_3
|THERMISTOR_3
|[[File:IC-Pin-in.png|frameless]]
|[[File:IC-Pin-in.png|frameless]]
|Signal for Thermistor located near SSD PMIC
|
|-
|-
|E1
|E1
Line 428: Line 425:
|3.3V_SS_PG1_XTAL
|3.3V_SS_PG1_XTAL
|
|
|Supply for 25MHz oscillator driver
|
|-
|-
|E2
|E2
Line 434: Line 431:
|3.3V_SS_PG2
|3.3V_SS_PG2
|
|
|Supply for the General purpose PLL cluster
|
|-
|-
|E3
|E3
Line 500: Line 497:
|THERMISTOR_1
|THERMISTOR_1
|
|
|Signal for Thermistor located between PSU spike and APU
|
|-
|-
|E17
|E17
Line 506: Line 503:
|THERMISTOR_2
|THERMISTOR_2
|
|
|Signal for Thermistor located on LED Board
|
|-
|-
|F3
|F3
Line 512: Line 509:
|D85_FC_TX0P
|D85_FC_TX0P
|
|
|PCI-e Gen3 RX+ from flash controller.
|
|-
|-
|F4
|F4
Line 518: Line 515:
|D85_FC_TX0N
|D85_FC_TX0N
|
|
|PCI-e Gen3 RX- from flash controller.
|
|-
|-
|F5
|F5
Line 554: Line 551:
|FAN_PWM_1
|FAN_PWM_1
|
|
|Fan speed PWM signal
|
|-
|-
|F14
|F14
Line 578: Line 575:
|GND
|GND
|[[File:IC-Pin-in.png|frameless]]
|[[File:IC-Pin-in.png|frameless]]
|ADC Ground reference
|Ground
|-
|-
|F18
|F18
Line 584: Line 581:
|3.3V_SS_PG1_XTAL
|3.3V_SS_PG1_XTAL
|
|
|ADC Supply reference
|
|-
|-
|G1
|G1
Line 590: Line 587:
|D85_FC_RX0P
|D85_FC_RX0P
|
|
|PCI-e Gen3 TX+ to flash controller.
|
|-
|-
|G2
|G2
Line 596: Line 593:
|D85_FC_RX0N
|D85_FC_RX0N
|
|
|PCI-e Gen3 TX- to flash controller.
|
|-
|-
|G3
|G3
Line 614: Line 611:
|1.15V_SS_PG2
|1.15V_SS_PG2
|
|
|Supply for PCI-e Gen 3 RX PHY
|
|-
|-
|G6
|G6
Line 620: Line 617:
|1.15V_SS_PG2
|1.15V_SS_PG2
|
|
|Supply for PCI-e Gen 3 TX PHY
|
|-
|-
|G7
|G7
Line 656: Line 653:
|BUZZER_PWM
|BUZZER_PWM
|
|
|Buzzer signal output
|
|-
|-
|G13
|G13
Line 668: Line 665:
|D100G_WIFI_PCIE_CLK_P
|D100G_WIFI_PCIE_CLK_P
|
|
|PCI-e Clock+ to wifi with Spread Spectrum Clocking.
|
|-
|-
|G15
|G15
Line 674: Line 671:
|D100G_WIFI_PCIE_CLK_N
|D100G_WIFI_PCIE_CLK_N
|
|
|PCI-e Clock- to wifi with Spread Spectrum Clocking.
|
|-
|-
|G16
|G16
Line 686: Line 683:
|D85_WIFI_RX0P
|D85_WIFI_RX0P
|
|
|PCI-e gen1 RX+ from Wifi module.
|
|-
|-
|G18
|G18
Line 692: Line 689:
|D85_WIFI_RX0N
|D85_WIFI_RX0N
|
|
|PCI-e gen1 RX- from Wifi module.
|
|-
|-
|H3
|H3
Line 698: Line 695:
|D100G_M2_PCIE_CLK_P
|D100G_M2_PCIE_CLK_P
|
|
|PCI-e Clock+ to M.2 slot
|
|-
|-
|H4
|H4
Line 704: Line 701:
|D100G_M2_PCIE_CLK_N
|D100G_M2_PCIE_CLK_N
|
|
|PCI-e Clock- to M.2 slot
|
|-
|-
|H5
|H5
Line 746: Line 743:
|3.3V_SS_PG2
|3.3V_SS_PG2
|
|
|Supply for PCI-e G1 clock PHYs and core
|
|-
|-
|H14
|H14
Line 752: Line 749:
|1.15V_SS_PG2
|1.15V_SS_PG2
|
|
|Supply for PCI-e G1 RX/TX PHYs
|
|-
|-
|H15
|H15
Line 1,310: Line 1,307:
|3.3V_SS_SUSB_PG3
|3.3V_SS_SUSB_PG3
|
|
|Supply for the USB Port 0/1 Core and PHY
|
|-
|-
|P12
|P12
Line 1,759: Line 1,756:
= Pictures =
= Pictures =


[[File:CXD90061GG.png|253x253px]]
[[File:CXD90061GG.png]]
[[File:CXD90061GG_Proto.png|452x452px]]
[[File:CXD90061GG_Proto.png]]
[[File:Image.png|frameless|252x252px]]
[[File:Image.png]]
[[File:Image2.png|254x254px]]
[[File:Image2.png]]
[[File:Image3.png|269x269px]]
[[File:Image3.png]]
Please note that all contributions to PS5 Developer wiki are considered to be released under the GNU Free Documentation License 1.2 (see PS5 Developer wiki:Copyrights for details). If you do not want your writing to be edited mercilessly and redistributed at will, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource. Do not submit copyrighted work without permission!

To protect the wiki against automated edit spam, we kindly ask you to solve the following hCaptcha:

Cancel Editing help (opens in new window)
Retrieved from "http://www.psdevwiki.com/ps5/CXD90061GG"