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* size of patapon is 574MB, size of locoroco 2 is 3.3GB
* size of patapon is 574MB, size of locoroco 2 is 3.3GB


* Crashing near sceGeListEnQueue means low vram??
= ELF fix by mysis =
* https://www.psx-place.com/threads/psp-emulation-on-ps4-early-stages-of-injecting-games-homebrew-on-discovered-psp-emulator.17830/#post-134501
* https://github.com/pink1stools/fix_elf


= Patches =
= Patches =
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**patchworkheroes
**patchworkheroes
**locoroco2
**locoroco2
**rondo (Castlevania: The Dracula X Chronicles?)
**rondo
**full
**full


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**oenter
**oenter
**ocancel
**ocancel
'''Additionally emulator check for title IDs:
'''
*NPUG80325 GOW Chains of Olympus
*NPEG00023 GOW Chains of Olympus
*NPHG00027 GOW Chains of Olympus
*NPUG80508 GOW Ghost of Sparta
*UCUS98617 Gangs of London
*UCES00113 Gangs of London
And do something when ID match, for now is unknown what exactly.
== Registers ==
With recent findings from user Scalerize we have now regs base. So we can see mapping from Get/Set registers lua functions. ;)
* GPR registers start at base + 0x288, since emu code set ra in jal opcode, we ca see that ra is at base + 304. So base for GPR regs is 0x200414D24 - (31 * 4). Which give us 0x200414CA8 for $zero reg, 0x200414CAC for $at, rest is already documented.
* '''Base is 0x200414A20''' ($zero reg - 0x288)
* Hi/Lo regs are located at base + 0x308/0x30C (0x200414D28 Lo/ 0x200414D2C Hi), based on GetHi/GetLo lua functions.
* FPR regs start a base + 0x32C (0x200414D4C), from $f00 up to $f31, 4 bytes (wasn't psp fpu able to work with doubles? but emu for sure use 32 bit regs). Based on Get/Set Fpr lua code.
* PC is at base + 0x314, already documented.
* First five VFPU extra registers ([http://hitmen.c02.at/files/yapspd/psp_doc/chap4.html#sec4.5.2 info]) are mapped to base + 0x5C0.
* VFPU 135 reg read just return 0x7772CEAB, it's not mapped anywhere.
* VFPU regs 136 to 139 read base + 0x558, and 140 to 143 read base + 0x564 (which are probably mapped to something important, maybe VFPU 128 bit regs.)
* Todo: VFPU registers, but i need to reverse instruction decoder to do that.
--[[User:Kozarovv|Kozarovv]] ([[User talk:Kozarovv|talk]]) 08:02, 22 June 2023 (CEST)
<br> Are C000 and E000 and R000 registers? --[[User:Scalerize|Scalerize]] ([[User talk:Scalerize|talk]]) 20:53, 22 June 2023 (CEST)
* All of them access the same register block. VFPU have really weird register mapping where first character is access way, first digit is register block number, second digit is "horizontal" number of register in block, and last digit is vertical number of register in block. One block is 4x4 size, and there is 8 blocks (0-7). Looks like VFPU registers are xxx414DE0 - xxx414FDF, but its unconfirmed for now. --[[User:Kozarovv|Kozarovv]] ([[User talk:Kozarovv|talk]]) 11:32, 23 June 2023 (CEST)
** Ok, regs are there. Confirmed in instruction decoder. Starting at 414DE0 one block is 0x40 long, so next block is 414E20, etc. --[[User:Kozarovv|Kozarovv]] ([[User talk:Kozarovv|talk]]) 11:41, 23 June 2023 (CEST)
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