Editing Syscon Hardware

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PS4 Syscon is codenamed '''Colwick'''. It is a custom Renesas RL78/G13.
PS4 Syscon is codenamed '''Colwick'''. It is a custom Renesas RL78/G13.
= Hardware revisions =
{| class="wikitable"
! Production Start Date (<=) || PS2 Mechacon !! PSP Syscon !! PS3 Syscon !! PS Vita Syscon !! PS4 Syscon !! Used IC/CPU Core
|-
| <abbr title="CVN-001, SAA-001, SAB-001">07/2013</abbr> || - || - ||- || - || COL || Renesas R5F100PL (RL78/G13, 100 pin)
|-
| <abbr title="SAC-001, SAD-001, SAD-002, SAD-003, SAE-001, SAE-002, SAE-003, SAE-004, HAC-001, NVA-001, NVB-003, NVB-004, NVG-001, NVG-002">04/2015</abbr> || - || - ||- || - || COL2 || Renesas R5F101LL (RL78/G13, 64 pin)
|}


= Pictures =
= Pictures =
Line 23: Line 13:
! Offset !! Size !! Description !! Notes
! Offset !! Size !! Description !! Notes
|-
|-
| 0x00000 || 0x20000 || Code Flash Area ||
| 0x00000 || 0x20000 || Code Area ||
|-
|-
| 0x20000 || 0xD0000 || Reserved || OCDROM is here
| 0x20000 || 0xD0000 || Reserved || OCDROM is here
|-
|-
| 0xF0000 || 0x800 || Special Function Registers 2 ||
| 0xF0000 || 0x800 || SFR Area ||
|-
|-
| 0xF0800 || 0x800 || Reserved (bootloader RAM) ||
| 0xF0800 || 0x800 || Reserved ||
|-
|-
| 0xF1000 || 0x1000 || Data Flash Area ||
| 0xF1000 || 0x1000 || Data Area ||
|-
|-
| 0xF2000 || 0xCF00 || Mirror || Mirror of a portion of Code Flash Area
| 0xF2000 || 0xCF00 || Mirror || Mirror of a portion of code area
|-
|-
| 0xFEF00 || 0xFE0 || RAM || Stack is usually at 0xFFE00.
| 0xFEF00 || 0xFE0 || RAM ||  
|-
|-
| 0xFFEE0 || 0x20 || General-Purpose Registers ||
| 0xFFEE0 || 0x20 || GPR ||
|-
|-
| 0xFFF00 || 0x100 || Special Function Registers ||
| 0xFFF00 || 0x100 || SFR 2nd Area ||
|}
|}


Line 114: Line 104:
! Name !! Description !! Notes
! Name !! Description !! Notes
|-
|-
| SOH || Start of OH - Command Frame Header || 0x01 Always
| SOH || Command Frame Header || 0x01 Always
|-
|-
| STX || Start of TX -  Data Frame Header || 0x02 Always
| STX || Data Frame Header || 0x02 Always
|-
|-
| LEN || LENgth - Length of info || In Command frame: length of COM + command info length / In Data frame: Data info length
| LEN || Length of info || In Command Frame: length of COM + command info length / In Data frame: Data info length
|-
|-
| COM || COMmand - Command number ||
| COM || Command number ||
|-
|-
| SUM || checkSUM - Checksum || checksum of command (initial byte (0x00) - LEN - COM - INFO ) / (initial byte (0x00) - LEN - DAT)
| SUM || Checksum || checksum of command (initial byte (0x00) - LEN - COM - INFO ) / (initial byte (0x00) - LEN - DAT)
|-  
|-  
| ETB || End of TB - Data frame footer || 0x17 Always  
| ETB || Footer of data frame || 0x17 Always  
|-
| ETX || End of TX - Command frame footer || 0x03 Always
|-
|}
 
= Pinout =
 
== 64-pin ==
{| class="wikitable"
|-
! Pin
! Description
! Notes
|-
| 1
| P120/ANI19
| power switch (USBHUB)
|-
| 2
| P43
| APU-RESET#
|-
| 3
| P42/TI04/TO04
| (HDR-A SPI-CS)
|-
| 4
| P41/TI07/TO07
| power switch (PSU-7)
|-
| 5
| P40/TOOL0
| -> HDR-A pin 22 (open circuit between pin and header)
|-
| 6
| RESET
| -> HDR-A pin 24
|-
| 7
| P124/XT2/EXCLKS
| pulldown?
|-
| 8
| P123/XT1
| power switch (PSU-5)
|-
| 9
| P137/INTP0
| testpoint?
|-
| 10
| P122/X2/EXCLK
| -> HDR-A pin 28 (4bit input-only, port 12)
|-
| 11
| P121/X1
| -> HDR-A pin 29 (4bit input-only, port 12)
|-
| 12
| REGC
| cap to GND
|-
| 13
| V SS
| GND
|-
| 14
| EVSS0
| GND
|-
| 15
| VDD
| Vcc
|-
| 16
| EVDD0
| Vcc
|-
| 17
| P60/SCLA0
| APU i2c dev 0xba
|-
| 18
| P61/SDAA0
| APU i2c dev 0xba
|-
| 19
| P62
| APU i2c dev 0x78/0x98
|-
| 20
| P63
| APU i2c dev 0x78/0x98
|-
| 21
| P31/TI03/TO03/INTP4/(PCLBUZ0)
| FAN-CTL
|-
| 22
| P77/KR7/INTP11/(TxD2)
| pulldown
|-
| 23
| P76/KR6/INTP10/(RxD2)
| N/A
|-
| 24
| P75/KR5/INTP9/SCK01/SCL01
| APU?
|-
| 25
| P74/KR4/INTP8/SI01/SDA01
| N/A
|-
| 26
| P73/KR3/SO01
| power switch (USBBRIDGE + HDD)
|-
| 27
| P72/KR2/SO21
| -> HDR-A pin 12 (HDR-A SPI-SO)
|-
| 28
| P71/KR1/SI21/SDA21
| (HDR-A SPI-SI)
|-
| 29
| P70/KR0/SCK21/SCL21
| -> HDR-A pin 10 (HDR-A SPI-CLK)
|-
| 30
| P06/TI06/TO06
| power switch (PSU-1)
|-
| 31
| P05/TI05/TO05
| N/A
|-
| 32
| P30/INTP3/RTC1HZ/SCK11/SCL11
| NC testpoint
|-
|-
| 33
| ETX || Command frame footer || 0x03 Always
| P50/INTP1/SI11/SDA11
| power switch (SB-1 + SB-2 + DDR3)
|-
|-
| 34
| P51/INTP2/SO11
| power switch (SB-0) (6pin near Wi-Fi + 8pin between SC/SB)
|-
| 35
| P52/(INTP10)
| testpoint?
|-
| 36
| P53/(INTP11)
| VR-SM_CLK
|-
| 37
| P54
| N/A
|-
| 38
| P55/(PCLBUZ1)/(SCK00)
| power switch (APU-2)
|-
| 39
| P17/TI02/TO02/(SO00)/(TxD0)
| N/A
|-
| 40
| P16/TI01/TO01/INTP5/(SI00)/(RxD0)
| SB-TP0 looks like SB -> SC interrupt line (INTP5)
|-
| 41
| P15/SCK20/SCL20/(TI02)/(TO02)
| SB-TP1 (SPI-CLK)
|-
| 42
| P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
| SB-TP2 (SPI-SI) + SC-P11 in a weird way? + elsewhere
|-
| 43
| P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
| SB-TP3 (SPI-SO)
|-
| 44
| P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05)
| -> HDR-A pin 15 (SC ucmd UART)
|-
| 45
| P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
| -> HDR-A pin 16 (SC ucmd UART)
|-
| 46
| P10/SCK00/SCL00/(TI07)/(TO07)
| SB-TP4 (SPI-CS)
|-
| 47
| P146
| NC
|-
| 48
| P147/ANI18
| power switch (HDMI-1)
|-
| 49
| P27/ANI7
| NC testpoint
|-
| 50
| P26/ANI6
| STM8-PWR pin 1 + HDR-C pin 8 (POWER#) (serial clock)
|-
| 51
| P25/ANI5
| STM8-EJECT pin 1 + HDR-C pin 7 (EJECT#)
|-
| 52
| P24/ANI4
| pulldown?
|-
| 53
| P23/ANI3
| pulldown?
|-
| 54
| P22/ANI2
| N/A
|-
| 55
| P21/ANI1/AVREFM
| NC testpoint
|-
| 56
| P20/ANI0/AVREFP
| N/A
|-
| 57
| P130
| power switch (PSU-6) (P130 is tied to sc-internal RESET)
|-
| 58
| P04/SCK10/SCL10
| i2c (PCIe clockgen smbus?)
|-
| 59
| P03/ANI16/SI10/RxD1/SDA10
| -> HDR-F pin 1 (i2c (PCIe clockgen smbus?))
|-
| 60
| P02/ANI17/SO10/TxD1
| -> HDR-F pin 2 (XXX did I fuckup the HDR-F mapping here?)
|-
| 61
| P01/TO00
| N/A
|-
| 62
| P00/TI00
| N/A
|-
| 63
| P141/PCLBUZ1/INTP7
| VR-VRDY1
|-
| 64
| P140/PCLBUZ0/INTP6
| VR-VRDY2
|}
|}


== 100-pin ==
= Pinout (100pin) =


{| class="wikitable sortable"
{| class="wikitable sortable"
Line 482: Line 206:
| 40    || P70        || -> HDR-A pin 10 (HDR-A SPI-CLK)
| 40    || P70        || -> HDR-A pin 10 (HDR-A SPI-CLK)
|-
|-
| 41    || P06        || power switch (PSU-1)
| 41    || P06        || power switch(PSU-1)
|-
|-
| 42    || P05        ||  
| 42    || P05        ||  
Line 510: Line 234:
| 54    || P50        || power switch (SB-1 + SB-2 + DDR3)
| 54    || P50        || power switch (SB-1 + SB-2 + DDR3)
|-
|-
| 55    || P51        || power switch (SB-0) (6pin near Wi-Fi + 8pin between SC/SB)
| 55    || P51        || power switch (SB-0) (6pin near wifi + 8pin between SC/SB)
|-
|-
| 56    || P52        || testpoint?
| 56    || P52        || testpoint?
Line 564: Line 288:
| 81    || P151        || power switch (PSU-3)
| 81    || P151        || power switch (PSU-3)
|-
|-
| 82    || P150        || Wi-Fi reset?
| 82    || P150        || WIFI reset?
|-
|-
| 83    || P27        || NC testpoint
| 83    || P27        || NC testpoint
Line 586: Line 310:
| 92    || P102        ||
| 92    || P102        ||
|-
|-
| 93    || P04        || i2c ([[PCIe]] clockgen smbus?)
| 93    || P04        || i2c (PCIE clockgen smbus?)
|-
|-
| 94    || P03        || -> HDR-F pin 1 (i2c ([[PCIe]] clockgen smbus?))
| 94    || P03        || -> HDR-F pin 1 (i2c (PCIE clockgen smbus?))
|-
|-
| 95    || P02        || -> HDR-F pin 2 (XXX did I fuckup the HDR-F mapping here?)
| 95    || P02        || -> HDR-F pin 2 (XXX did I fuckup the HDR-F mapping here?)
Line 604: Line 328:
|}
|}


= Glitching, Dumping & Flashing =
= Dump and Restore =
 
== Method 1 ==


Based on the attack outlined by Fail0verflow [https://fail0verflow.com/blog/2018/ps4-syscon] '''Wildcard''' designed the following glitch using a Teensy: [https://github.com/VV1LD/SYSGLITCH].
We are able to make a 1:1 copy of a PS4 Syscon and put it on another chip. This allows to install a dump of a PS4 Syscon to a brand new chip then swap it.


Using '''Wildcard''''s shellcode but using a different methodology on his GitHub, you can copy the original Syscon and dump it to a new Renesas chip with comparatively greater ease. '''Guide available on BwE's GitHub.'''
This is often used in firmware revert [[Downgrade]] method to avoid having to flash the same chip each time one wants to revert firmware but instead only have to swap the chips.


You can also flash to the original SCE syscon using a different shellcode but this is a commercial product sold by [[User:BwE]].
= Syscon glitching =


== Method 2 ==
By glitching Syscon, it is possible to dump its EEPROM, including NVS.


See Abkarino's publications.
To be documented.
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